ASIC Power & Physical Design Engineer (SoC / RTL / PPA) | Remote

Position: Senior ASIC Power Engineer

Type: Full-time (W2, Contingent Role)

Compensation: $100–$135 per hour

Location: Sunnyvale, CA, USA

Commitment: Full-time

Role Responsibilities

• Perform power analysis and optimization for ASIC designs in AR/VR products
• Conduct RTL and netlist-level power analysis and PPA optimization using tools like Fusion Compiler
• Set up, run, debug, and analyze ASIC design flows including synthesis, place & route, timing, and power
• Develop scripts (Python, Tcl, etc.) for report processing, data extraction, and analysis
• Implement and validate RTL blocks and power intent (UPF) specifications
• Analyze power trade-offs across design and backend implementation stages
• Document methodologies and communicate findings clearly to cross-functional teams
  
  

Requirements

• Strong years of experience in ASIC power, CAD, or physical design engineering
• Strong experience with power estimation tools, synthesis, and physical design flows
• Proficiency in scripting (Python, Tcl, Perl) and data analysis
• Solid understanding of low-power design techniques and UPF methodologies
• Bachelor’s degree in Electrical Engineering, Computer Science, or equivalent experience
• Strong analytical and problem-solving skills with clear communication abilities
  
  

Application Process (Takes 20 Mins)

• Upload your resume.
• Complete an interview.
• Submit a short form.