ASIC Physical Design Lead

We're partnering with an industry-leading technology company seeking an experienced Advanced ASIC Physical Design Lead to drive the development of next-generation mixed-signal ASICs used in cutting-edge semiconductor test and automation platforms.
This is a highly visible technical leadership role where you'll own the physical design flow from RTL to GDSII, influence chip architecture, mentor engineers, and help deliver first-pass silicon success at advanced technology nodes.
What You'll Do
Lead and mentor a team of physical design engineers
Drive physical design architecture, floorplanning, timing budgets, and power planning
Own RTL-to-netlist activities including synthesis, CDC, LEC, and STA
Support hands-on place-and-route (P&R) for high-performance designs
Collaborate with cross-functional teams including digital, analog, and system architects
Integrate complex IPs including PCIe, DDR5/DDR6, UFS, and SerDes
Drive signoff closure for timing, DRC/LVS, and EM/IR requirements
Develop and improve physical design methodologies, flows, and automation
What We're Looking For
10+ years of ASIC Physical Design experience
Proven experience with advanced process nodes (16nm and below)
Strong expertise in RTL-to-GDSII implementation and timing closure
Deep understanding of STA, constraints development, and signoff methodologies
Experience with high-speed IP integration (PCIe, DDR5/DDR6, UFS, SerDes)
Proficiency with Cadence or similar EDA tools
Scripting experience with Tcl, Python, and/or Make
BS or MS in Electrical Engineering or a related field
Why Consider This Opportunity?
Work on complex, advanced-node silicon designs
High level of technical ownership and visibility
Collaborative, engineering-driven environment
Competitive compensation, bonus potential, and comprehensive benefits
Significant growth and leadership opportunities

Salary Range: $180k - $300k + bonus potential
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