ASIC Physical Design Engineer

We are hiring an experienced ASIC Top‑Level Floorplan Physical Design Engineer to join a high‑impact ASIC team at a leading semiconductor company.
In this role, you will work on advanced AI and PCIe switch products and own top‑level physical design from RTL through tapeout.

What You Will Do
Own full‑chip floorplanning including die size estimation and partitioning
Define top‑level clock distribution and deliver physical partitions
Resolve physical integration challenges related to chip assembly
Partner with package teams on I/O planning, bump mapping, and RDL strategy
Collaborate with design and methodology teams across the development cycle
Develop and improve floorplanning methodologies and internal flows
Evaluate internal and third‑party IP from a physical design perspective
Required Experience
Bachelor’s degree with 8+ years or Master’s degree with 6+ years of experience
Proven experience in top‑level floorplanning and full‑chip physical design
Strong background in die sizing, partitioning, clocking, and pin assignment
Experience with large SoCs and complex subsystems
Hands‑on experience resolving chip‑level DRC, LVS, and EM or IR issues
Successful tapeout experience at advanced process nodes
Technical Background
Experience with high‑speed and complex IP such as DDR, SerDes, HBM, and PCIe
Familiarity with chiplet or die‑to‑die based designs
Experience with bump planning, RDL routing, and multi‑voltage domains
Strong understanding of hierarchical physical design and power grid planning
Experience with structured clocking and top‑level placement strategies
Proficiency in scripting languages such as Python, Tcl, or Perl
What Makes This Role Unique
End‑to‑end ownership of top‑level physical design
Work on cutting‑edge AI and high‑performance networking silicon
Exposure to advanced nodes and complex packaging technologies
High visibility role with strong cross‑functional influence
Show more Show less