ASIC Low Power Engineer

ASIC Low Power Expert

We are seeking an experienced ASIC Low Power Expert to join our team and drive power optimization strategies across all our SoC designs. The ideal candidate will have deep expertise in low-power methodologies, power intent specification, power estimation methodologies and advanced techniques for reducing dynamic and static power in high-performance ASICs.

Location: Bangalore, KA. India

Required Qualification
Bachelor’s or Master’s degree in Electronics Engineering or VLSI
8+ years of experience in ASIC/SoC design with a focus on low-power techniques, Power estimation and debug of Si power

Skillset Requirements
Excellent understanding of Power Budgeting, Power Analysis, Power Estimation and Low Power design and implementation techniques
Expertise in RTL design and synthesis tools (e.g., Synopsys DC/FC, Cadence Genus).
Expert in working with power estimation tools and methodologies both at RTL and Netlist level
Good knowledge of UPF/CPF standards and power-aware design flows
Solid understanding of clock/reset architecture and power management controllers
Exposure to ARM-based SoC architectures and AMBA protocols
Knowledge of advanced process nodes and their impact on power optimization
Post Si power measurement analysis and debug
Excellent problem-solving and communication skills to work with cross functional teams

Key Responsibilities
Work with vendors, designers and system/marketing team to define Power Budget for the ASIC
Define and implement Power estimation flows and methodologies
Analyse the power issues – from Architecture to Implementation and Si
Define and implement low-power architecture strategies for ASIC/SoC designs
Collaborate with RTL, DV, synthesis, and physical design teams to ensure power goals are met
Perform power analysis at RTL, gate-level, and post-layout stages
Optimize clock gating, power gating, DVFS, and multi-voltage domain implementations.
Develop and maintain UPF/CPF-based power intent specifications
Work closely with verification teams to validate low-power features and ensure functional correctness.
Support sign-off activities including power-aware simulations and checks
Work with Si validation teams on power measurement, Si power debug and optimization
Work with fab/technology team for process tunning to reduce Si power
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