ASIC Engineering Lead

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Hello,

Greetings from Clifyx.

Position 3: ASIC Engineering Technical Leader

Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing)

methodology in silicon one chips

Design & implement robust and reusable RTL with CDC/RDC considerations
Spec comprehensive CDC/RDC check flows and work with CAD team to implement
Review and approve CDC/RDC constraints and waivers
Perform static glitch analysis

Improve design with prevention of static glitch harzad

Bachelor''s or Master''s degree on Electrical Engineering with at least 10 years of experience on

ASIC chip design

RTL development skills and experiences
Solid understanding on CDC/RDC concepts and relevant design implementation
Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
Solid understanding on static glitch harzads and experience on the relevant analysis on

synthesis optimized gate netlists

Preferred Qualifications

Experiences on Static Timing Analysis
Experiences on VCS simulation SVA (SystemVerilog Assertions)

Thanks, Regards

Vishal Swami
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