ASIC Engineer

Key Responsibilities:

• Deploy and validate SoCs on ZEBU and HAPS platforms
• Work on PCIe, LPDDR, and ONFI controller/IP validation across pre-silicon phases
• Perform PCIe bring-up, debugging, and interoperability testing
• Collaborate with global teams for PCIe/LPDDR implementation and debug activities
• Debug RTL, FPGA, hardware, and system-level issues
• Generate debug logs, root-cause analysis, and validation reports

🔹 Required Skills:
✅ Hands-on experience with ZEBU Emulation Platform (Mandatory)
✅ Strong knowledge of Synopsys ProtoCompiler Flow
✅ Xilinx Ultrascale/Ultrascale+ FPGA implementation experience
✅ Vivado Design Suite expertise
✅ FPGA debugging using ChipScope/ILA
✅ Experience with PCIe Gen3/4/5/6, LPDDR, and/or ONFI
✅ Understanding of SoC architecture and pre-silicon validation methodologies
✅ Verilog RTL debugging and development experience
✅ Knowledge of SERDES configuration and high-speed interfaces
🔹 Preferred Experience:
• HAPS Prototyping Platforms
• PCIe/NVMe architecture
• Interaction with Xilinx and Synopsys teams
• Firmware and SoC validation/debug activities
🎓 Qualification:

Bachelor’s or Master’s Degree in Engineering
If you have strong hands-on expertise in ZEBU, FPGA prototyping, PCIe validation, and pre-silicon SoC bring-up, we'd love to connect.

📩 Interested candidates can share their updated resume or reach out directly. shreevidya.e@pozibility.in
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