ASIC DFT Engineer

Title - Lead ASIC DFT Engineer
Location – Remote (must be aligned with PST time zone)
Bill Rate –$110/hr. - $130/hr. C2C


Job Descriptio
nKey skills for Lead ASIC DFT

:
please see these key words of in the project description for the profile consideration
. “SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax

“
Experie
nce10+ years of hands-on experience in ASIC Design-for-Test (D

FT)
Role Sum
maryWe are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon iss
ues.The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yi

eld.
Key Responsibil
itiesLead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC des
igns.Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testabi
lity.Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up ph
ases.Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon is
sues.Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing anal
ysis.Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation is
sues.Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/d
ebug.Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integra
tion.Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test qua
lity.Act as a technical escalation point for advanced DFT and post-silicon debug is
sues.Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automa
tion.Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug producti

vity.
Required Skills & Qualific
ationsStrong hands-on experience in ASIC DFT with end-to-end owne
rship.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage con
cepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon
debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA
tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC ana
lysis.Experience with MBIST implementation and verification; SMS experience pref
erred.Experience with scan architecture and scan chain stitching; Tessent/SSN experience pref
erred.Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implement
ation.Proven post-silicon debug and silicon bring-up exper
ience.Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration chall
enges.Strong communication skills and the ability to work independently with minimal ra

mp-up.
Preferred Exp
erienceMBIST post-silicon vali
dation.ATPG simulations and fault coverage
debug.DFT RTL, DFD, DFT verification, and IP-level DFT integ
ration.DFT SDC creation and DFT timing closure s
upport.Boundary scan, iJTAG, SSN, and design-for-debug methodo
logies.TCL/PERL scripting for DFT automation, reporting, and
debug.Experience working across multiple ASIC technology nodes and complex product development
cycles.Familiarity with yield learning, diagnosis, and manufacturing test optimi

zation.
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