MA
ASIC DFT Engineer
Accepting applicationsMobile Apps US · United States
Contract Mid_senior ASICATPGBoundary ScanCadenceDFT
Posted
6d ago
Category
Test
Experience
Mid_senior
Country
United States
Lead ASIC DFT Engineer
Location: Remote (Must work PST hours)
Visa: Any Visa
Experience: 10+ Years
Role Summary
Seeking a Lead ASIC DFT Engineer with strong expertise in ASIC/SoC Design-for-Test, including DFT architecture, Scan, ATPG, MBIST/LBIST, JTAG, Boundary Scan, and Post-Silicon Validation. The candidate will lead DFT implementation, debug, sign-off, and silicon bring-up activities for complex chip designs.
Key Responsibilities
Lead DFT architecture, implementation, verification, and sign-off.
Drive Scan Insertion, Scan Stitching, Scan Compression, and ATPG flows.
Own MBIST/LBIST integration, verification, and debug.
Perform DFT debug, failure analysis, diagnosis, and fault coverage closure.
Develop DFT constraints (SDC), timing analysis, and DRC checks.
Support ATPG pattern generation, simulations, and silicon validation.
Work on JTAG, Boundary Scan, iJTAG, SSN, and IP-level DFT integration.
Collaborate with RTL, STA, Physical Design, Verification, and Validation teams.
Mentor engineers and develop automation using TCL, Perl, or Python.
Required Skills
Strong ASIC DFT experience with end-to-end ownership.
Expertise in SCAN, ATPG, MBIST, LBIST, JTAG, Boundary Scan, Silicon Debug.
Experience with SDF, SDC, Timing Simulations, DRC Analysis.
Hands-on with TetraMAX, DFTMAX, Tessent, Synopsys, Cadence, Siemens/Mentor tools.
Experience in Pattern Retargeting, Pattern Porting, Diagnosis, Post-Silicon Validation.
Knowledge of RTL, Synthesis, LEC, PLLs, and Physical Design flows.
Experience with large SoC designs and hierarchical DFT methodologies.
Preferred Skills
MBIST Post-Silicon Validation
ATPG Simulations & Fault Coverage Debug
DFT Verification and IP-Level Integration
iJTAG, SSN, Design-for-Debug
TCL/Perl/Python Automation
Yield Learning and Manufacturing Test Optimization
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Location: Remote (Must work PST hours)
Visa: Any Visa
Experience: 10+ Years
Role Summary
Seeking a Lead ASIC DFT Engineer with strong expertise in ASIC/SoC Design-for-Test, including DFT architecture, Scan, ATPG, MBIST/LBIST, JTAG, Boundary Scan, and Post-Silicon Validation. The candidate will lead DFT implementation, debug, sign-off, and silicon bring-up activities for complex chip designs.
Key Responsibilities
Lead DFT architecture, implementation, verification, and sign-off.
Drive Scan Insertion, Scan Stitching, Scan Compression, and ATPG flows.
Own MBIST/LBIST integration, verification, and debug.
Perform DFT debug, failure analysis, diagnosis, and fault coverage closure.
Develop DFT constraints (SDC), timing analysis, and DRC checks.
Support ATPG pattern generation, simulations, and silicon validation.
Work on JTAG, Boundary Scan, iJTAG, SSN, and IP-level DFT integration.
Collaborate with RTL, STA, Physical Design, Verification, and Validation teams.
Mentor engineers and develop automation using TCL, Perl, or Python.
Required Skills
Strong ASIC DFT experience with end-to-end ownership.
Expertise in SCAN, ATPG, MBIST, LBIST, JTAG, Boundary Scan, Silicon Debug.
Experience with SDF, SDC, Timing Simulations, DRC Analysis.
Hands-on with TetraMAX, DFTMAX, Tessent, Synopsys, Cadence, Siemens/Mentor tools.
Experience in Pattern Retargeting, Pattern Porting, Diagnosis, Post-Silicon Validation.
Knowledge of RTL, Synthesis, LEC, PLLs, and Physical Design flows.
Experience with large SoC designs and hierarchical DFT methodologies.
Preferred Skills
MBIST Post-Silicon Validation
ATPG Simulations & Fault Coverage Debug
DFT Verification and IP-Level Integration
iJTAG, SSN, Design-for-Debug
TCL/Perl/Python Automation
Yield Learning and Manufacturing Test Optimization
Show more Show less