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ASIC Design Verification Engineer - PQAngels
Accepting applicationsPQAngels Technologies Pvt Ltd · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICDDRPCIEPythonRTL
Posted
6d ago
Category
Design
Experience
Mid_senior
Country
India
Company Description PQAngels Technologies is a specialized in building high-performance engineering teams for the Post Quantum era of innovation. The company connects cutting-edge technology organizations with highly skilled professionals in Semiconductors, Cloud Computing, and Data Storage ecosystems. PQAngels Technologies focuses on niche engineering roles, enabling clients to innovate faster while offering candidates access to advanced projects and career growth. Applicants can expect to work with leading global tech companies and be part of teams driving next-generation hardware and software solutions.
Role Description The ASIC Design Verification Engineer – PQAngels will be responsible for verifying complex ASIC designs using industry-standard methodologies and tools. Day-to-day activities include developing verification plans, creating and maintaining test benches, writing test cases, performing functional and formal verification, and analyzing coverage metrics. The role involves close collaboration with RTL design engineers and architects to understand specifications, identify corner cases, and debug design and verification issues. The engineer will document findings, contribute to process improvements, and ensure that designs meet performance, reliability, and quality requirements. This is a full-time, on-site role based in the Greater Bengaluru Area. Or Direct Apply : https://pqangelstech.com/ Or Mail: Careers@pqangelstech.com
Requirements
Strong functional verification skills, including experience with test bench development, test case creation, coverage analysis, and verification methodologies (e.g., UVM or similar).
Proficiency in formal verification techniques and tools, with the ability to define properties, analyze results, and complement simulation-based verification.
Solid understanding of RTL design concepts and hardware description languages (such as Verilog or SystemVerilog), with the ability to review and collaborate on design implementation.
Good grasp of computer architecture fundamentals, including pipelines, memory subsystems, interfaces, and performance considerations relevant to ASIC design.
Strong debugging skills for identifying, isolating, and resolving design and verification issues, using simulation, waveform analysis, and regression results.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Experience with industry-standard EDA tools for simulation, formal verification, and linting; familiarity with version control and scripting (e.g., Python, Shell) is an advantage.
Ability to work collaboratively in cross-functional engineering teams, communicate complex technical concepts clearly, and manage tasks with attention to detail.
Prior experience in PCIE ,DDR, USB, UCIE ASIC or SoC projects, particularly in semiconductor or related domains, is highly beneficial.
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Role Description The ASIC Design Verification Engineer – PQAngels will be responsible for verifying complex ASIC designs using industry-standard methodologies and tools. Day-to-day activities include developing verification plans, creating and maintaining test benches, writing test cases, performing functional and formal verification, and analyzing coverage metrics. The role involves close collaboration with RTL design engineers and architects to understand specifications, identify corner cases, and debug design and verification issues. The engineer will document findings, contribute to process improvements, and ensure that designs meet performance, reliability, and quality requirements. This is a full-time, on-site role based in the Greater Bengaluru Area. Or Direct Apply : https://pqangelstech.com/ Or Mail: Careers@pqangelstech.com
Requirements
Strong functional verification skills, including experience with test bench development, test case creation, coverage analysis, and verification methodologies (e.g., UVM or similar).
Proficiency in formal verification techniques and tools, with the ability to define properties, analyze results, and complement simulation-based verification.
Solid understanding of RTL design concepts and hardware description languages (such as Verilog or SystemVerilog), with the ability to review and collaborate on design implementation.
Good grasp of computer architecture fundamentals, including pipelines, memory subsystems, interfaces, and performance considerations relevant to ASIC design.
Strong debugging skills for identifying, isolating, and resolving design and verification issues, using simulation, waveform analysis, and regression results.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related field.
Experience with industry-standard EDA tools for simulation, formal verification, and linting; familiarity with version control and scripting (e.g., Python, Shell) is an advantage.
Ability to work collaboratively in cross-functional engineering teams, communicate complex technical concepts clearly, and manage tasks with attention to detail.
Prior experience in PCIE ,DDR, USB, UCIE ASIC or SoC projects, particularly in semiconductor or related domains, is highly beneficial.
Show more Show less