GR
ASIC Design for Test Engineer
Accepting applicationsGood2go Recruiter · United States
Full-Time Entry ARMASICATPGBISTBoundary Scan
Posted
4d ago
Category
Test
Experience
Entry
Country
United States
ASIC Design for Test (DFT) EngineerAbout the Role
Good2go Recruiter is seeking an experienced ASIC Design for Test (DFT) Engineer to join an innovative semiconductor engineering team. In this role, you will be responsible for defining, implementing, and validating DFT architectures for complex ASIC and SoC designs. You will work closely with design, verification, physical design, and silicon validation teams to ensure high test coverage, manufacturability, and production readiness.
This position offers the opportunity to work on advanced semiconductor technologies and large-scale ASIC designs in a collaborative, engineering-focused environment.
Key Responsibilities
Develop and implement DFT architectures for ASIC and SoC designs.
Design and integrate scan chains, scan compression, MBIST, boundary scan (JTAG/BSCAN), and other test structures.
Generate, validate, and optimize ATPG test patterns.
Analyze and improve stuck-at, transition, and fault coverage metrics.
Develop and validate test timing constraints.
Perform logic simulation and verification of test patterns.
Support silicon bring-up, tester debug, and post-silicon validation activities.
Collaborate with design, verification, and physical design teams throughout the ASIC development lifecycle.
Investigate and resolve DFT-related issues impacting coverage, timing, or silicon testability.
Support manufacturing test development and yield improvement efforts.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in ASIC, SoC, or semiconductor design engineering.
Strong experience with Design for Test (DFT) methodologies, including:
Scan Insertion
Scan Compression
ATPG
MBIST
Boundary Scan (JTAG/BSCAN)
Macro Test Development
Experience with industry-standard DFT tools such as Synopsys, Siemens/Mentor Tessent, Cadence, or equivalent.
Experience performing Static Timing Analysis (STA) for DFT and test timing validation.
Experience with logic simulation tools and test pattern validation.
Understanding of ASIC design flow from RTL through silicon validation.
Strong problem-solving, debugging, communication, and teamwork skills.
Preferred Qualifications
Experience with large-scale ASIC or SoC designs.
Experience with ARM-based SoC architectures.
Experience supporting silicon bring-up and tester debug activities.
Familiarity with advanced process technologies and production test environments.
Experience with fault coverage analysis and test optimization techniques.
Citizenship Requirement
Due to ITAR compliance requirements, applicants must be either:
U.S. Citizens, or
U.S. Permanent Residents (Green Card Holders)
Benefits
We offer a comprehensive benefits package designed to support your professional growth and personal well-being:
Immediate vesting in 401(k) with a 10% employer contribution
Generous Paid Time Off (PTO)
Medical insurance plans, including employer HSA contributions
Dental coverage with 100% employer-paid premium under the basic plan
Vision insurance
Employer-paid basic life insurance
Optional supplemental life insurance
Employer-paid short-term and long-term disability coverage
Flexible and collaborative work environment
Opportunities to work on cutting-edge semiconductor technologies
Equal Opportunity Employer
Good2go Recruiter is an Equal Opportunity Employer and is committed to creating an inclusive workplace. We consider all qualified applicants without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, genetic information, or any other protected status under applicable federal, state, or local laws.
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Good2go Recruiter is seeking an experienced ASIC Design for Test (DFT) Engineer to join an innovative semiconductor engineering team. In this role, you will be responsible for defining, implementing, and validating DFT architectures for complex ASIC and SoC designs. You will work closely with design, verification, physical design, and silicon validation teams to ensure high test coverage, manufacturability, and production readiness.
This position offers the opportunity to work on advanced semiconductor technologies and large-scale ASIC designs in a collaborative, engineering-focused environment.
Key Responsibilities
Develop and implement DFT architectures for ASIC and SoC designs.
Design and integrate scan chains, scan compression, MBIST, boundary scan (JTAG/BSCAN), and other test structures.
Generate, validate, and optimize ATPG test patterns.
Analyze and improve stuck-at, transition, and fault coverage metrics.
Develop and validate test timing constraints.
Perform logic simulation and verification of test patterns.
Support silicon bring-up, tester debug, and post-silicon validation activities.
Collaborate with design, verification, and physical design teams throughout the ASIC development lifecycle.
Investigate and resolve DFT-related issues impacting coverage, timing, or silicon testability.
Support manufacturing test development and yield improvement efforts.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in ASIC, SoC, or semiconductor design engineering.
Strong experience with Design for Test (DFT) methodologies, including:
Scan Insertion
Scan Compression
ATPG
MBIST
Boundary Scan (JTAG/BSCAN)
Macro Test Development
Experience with industry-standard DFT tools such as Synopsys, Siemens/Mentor Tessent, Cadence, or equivalent.
Experience performing Static Timing Analysis (STA) for DFT and test timing validation.
Experience with logic simulation tools and test pattern validation.
Understanding of ASIC design flow from RTL through silicon validation.
Strong problem-solving, debugging, communication, and teamwork skills.
Preferred Qualifications
Experience with large-scale ASIC or SoC designs.
Experience with ARM-based SoC architectures.
Experience supporting silicon bring-up and tester debug activities.
Familiarity with advanced process technologies and production test environments.
Experience with fault coverage analysis and test optimization techniques.
Citizenship Requirement
Due to ITAR compliance requirements, applicants must be either:
U.S. Citizens, or
U.S. Permanent Residents (Green Card Holders)
Benefits
We offer a comprehensive benefits package designed to support your professional growth and personal well-being:
Immediate vesting in 401(k) with a 10% employer contribution
Generous Paid Time Off (PTO)
Medical insurance plans, including employer HSA contributions
Dental coverage with 100% employer-paid premium under the basic plan
Vision insurance
Employer-paid basic life insurance
Optional supplemental life insurance
Employer-paid short-term and long-term disability coverage
Flexible and collaborative work environment
Opportunities to work on cutting-edge semiconductor technologies
Equal Opportunity Employer
Good2go Recruiter is an Equal Opportunity Employer and is committed to creating an inclusive workplace. We consider all qualified applicants without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, genetic information, or any other protected status under applicable federal, state, or local laws.
Show more Show less