AT

ASIC Design-for-Test (DFT)

Accepting applications

Accord Technologies Inc · San Jose, United States, North America

Full-Time Entry ASICATPGBISTCadenceDFT
Posted
9 Apr
Category
Test
Experience
Entry
Country
United States
Role: Lead ASIC DFT Engineer

Location: San Jose, CA

Work Setup: Remote, PST time zone

Nbr of openings: 4 positions.

Visa type: Any Visa who can work in PST time zone

Position type: W2 or C2C

Mandatory Skills

DFT Architecture definition. – Must

Full chip / Sub system level DFT activities – Must

Scan & compression (EDT) implementation

LBIST implementation and verification – any BIST exp

Coverage improvements (Spyglass work)

ATPG

Experience Required

  • 10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

Key Skills Required

  • Strong hands-on ASIC DFT experience with end-to-end ownership
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
  • Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
  • Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
  • MBIST implementation and verification; SMS experience preferred
  • Tessent/SSN experience preferred
  • Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
  • Post-silicon debug and silicon bring-up experience

I Need Skill Metrics On

TCL, PERL, or Python scripting experience is highly preferred

  • DFT Architecture
  • Scan & compression(EDT) implementation
  • LBIST implementation and verification
  • Coverage improvements (Spyglass work)
  • ATPG sims - timing & no timing.
  • Full chip / Sub system level DFT activities.

Please prioritize this requirement and send relevant profiles at the earliest possible opportunity.

Thank you, and I look forward to your quick support.