VE
ASIC Design Engineer
Accepting applicationsV Engineering LLC · San Jose, CA
Full-Time Entry ASICCadenceMentorPerlPython
Posted
22h ago
Category
Design
Experience
Entry
Country
United States
Company Description V Engineering LLC is a leading staffing organization focused on connecting businesses with highly qualified technical talent. For more than a decade, the company has maintained a strong global client and candidate base, supported by a high customer retention rate. Its team of trained professionals leverages modern tools and methods to efficiently bridge the gap between employers and candidates. V Engineering LLC emphasizes a values-driven work culture and strong ethics, aiming to consistently match the right talent with the right opportunities. Applicants can expect a professional, collaborative environment with a focus on long-term success for both clients and engineers.
Role Description The ASIC Design Engineer role is a full-time, on-site position based in San Jose, CA. The engineer will be responsible for developing and implementing RTL designs, performing logic design, and collaborating on physical design integration for complex ASIC projects. Daily tasks include writing and optimizing RTL code, conducting formal verification, reviewing design specifications, and working closely with cross-functional teams such as verification, physical design, and architecture. The role also involves participating in design reviews, resolving design and timing issues, and ensuring that deliverables meet performance, power, and area requirements. The engineer will contribute to continuous improvement of design flows and best practices within the team.
Qualifications
Strong foundation in digital Logic Design and ASIC system architecture, with the ability to interpret and translate specifications into robust designs.
Hands-on experience with RTL Design and RTL Coding using industry-standard languages (e.g., Verilog, SystemVerilog, or VHDL).
Knowledge of Physical Design concepts and close collaboration experience with back-end teams on synthesis, timing closure, and floorplanning.
Proficiency in Formal Verification techniques and tools to verify functional correctness of RTL and support sign-off quality.
Relevant experience with EDA tools (e.g., Synopsys, Cadence, Mentor) and scripting skills in Python, Perl, or Tcl for automation.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Strong analytical and problem-solving abilities, attention to detail, and the capacity to collaborate effectively in a multidisciplinary team.
Excellent written and verbal communication skills, with the ability to document designs and present technical information clearly.
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Role Description The ASIC Design Engineer role is a full-time, on-site position based in San Jose, CA. The engineer will be responsible for developing and implementing RTL designs, performing logic design, and collaborating on physical design integration for complex ASIC projects. Daily tasks include writing and optimizing RTL code, conducting formal verification, reviewing design specifications, and working closely with cross-functional teams such as verification, physical design, and architecture. The role also involves participating in design reviews, resolving design and timing issues, and ensuring that deliverables meet performance, power, and area requirements. The engineer will contribute to continuous improvement of design flows and best practices within the team.
Qualifications
Strong foundation in digital Logic Design and ASIC system architecture, with the ability to interpret and translate specifications into robust designs.
Hands-on experience with RTL Design and RTL Coding using industry-standard languages (e.g., Verilog, SystemVerilog, or VHDL).
Knowledge of Physical Design concepts and close collaboration experience with back-end teams on synthesis, timing closure, and floorplanning.
Proficiency in Formal Verification techniques and tools to verify functional correctness of RTL and support sign-off quality.
Relevant experience with EDA tools (e.g., Synopsys, Cadence, Mentor) and scripting skills in Python, Perl, or Tcl for automation.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
Strong analytical and problem-solving abilities, attention to detail, and the capacity to collaborate effectively in a multidisciplinary team.
Excellent written and verbal communication skills, with the ability to document designs and present technical information clearly.
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