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ASIC Design Engineer
Accepting applicationsLumicity · San Jose, CA
Full-Time Mid_senior ASICCadenceEthernetGenusPCIe
Posted
23 Apr
Category
Design
Experience
Mid_senior
Country
United States
Senior ASIC Digital Design Engineer (Front-End)
Located on-site in San Jose, CA
Overview:
This is an exciting opportunity to work on high-speed digital integrated circuits for a startup who have a groundbreaking technology and have raised over $100million in funding. You will be working on High-Speed Digital Design, RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for the companies next generation products.
Essential Skills:
B.S. or M.S. in Electrical Engineering, Computer Engineering or similar
Experience working with Hardware Description Languages such as Verilog or SystemVerilog
A strong background working on Digital ASIC Design with the understanding of complete ASIC design flow from specification to tape-out.
Must have worked with Cadence or Synopsys Electronic Design Automation tools such as Tempus, PrimeTime, Genus, Design Compiler, Formality or JasperGold
Scripting experience with either Python, TCL or Perl
Experience working on Static Timing Analysis, Synopsys Timing Constraints, Clock Domain/Reset Domain
Preferred Skills (Not Essential):
High-Speed Interfaces (Ethernet, SerDes, PCIe etc.)
Working with protocols for Optical Communications
Digital Data Communication techniques including scrambling or forward error correction (FEC)
Company Benefits:
401K
Bonus
Stock/Equity
Full Premium Healthcare
Show more Show less
Located on-site in San Jose, CA
Overview:
This is an exciting opportunity to work on high-speed digital integrated circuits for a startup who have a groundbreaking technology and have raised over $100million in funding. You will be working on High-Speed Digital Design, RTL Design and Coding, Clock Domain Crossing, Synthesis and Timing Closure for the companies next generation products.
Essential Skills:
B.S. or M.S. in Electrical Engineering, Computer Engineering or similar
Experience working with Hardware Description Languages such as Verilog or SystemVerilog
A strong background working on Digital ASIC Design with the understanding of complete ASIC design flow from specification to tape-out.
Must have worked with Cadence or Synopsys Electronic Design Automation tools such as Tempus, PrimeTime, Genus, Design Compiler, Formality or JasperGold
Scripting experience with either Python, TCL or Perl
Experience working on Static Timing Analysis, Synopsys Timing Constraints, Clock Domain/Reset Domain
Preferred Skills (Not Essential):
High-Speed Interfaces (Ethernet, SerDes, PCIe etc.)
Working with protocols for Optical Communications
Digital Data Communication techniques including scrambling or forward error correction (FEC)
Company Benefits:
401K
Bonus
Stock/Equity
Full Premium Healthcare
Show more Show less