WR

ASIC Design Engineer-9+Years

Accepting applications

WiseCraft Recruitment VLSI Services · Hyderabad, Telangana, India

Full-Time Entry VerilogSystemVerilogMicroarchitectureRTLSynthesis
Estimated market salary
₹19-33 LPA

This is a SiliconBoard market estimate, not an employer-posted salary.

Posted
2d ago
Category
Design
Experience
Entry
Country
India
🚀 Hiring Alert | ASIC Design Engineer – Digital Design 🚀
📍 Location: Hyderabad
🏢 Industry: NXP Semiconductors
👨‍💻 Experience: 9+ Years

Role :

We are seeking an experienced RTL Designer with strong expertise in micro-architecture development, RTL design, integration, and implementation of complex digital blocks/subsystems. The ideal candidate will have a proven track record of translating architectural specifications into high-quality RTL, driving designs from concept through synthesis and silicon bring-up, and collaborating closely with architecture, verification, DFT, physical design, firmware, and system teams.

The role requires deep knowledge of System Verilog/Verilog RTL design, digital design fundamentals, clock/reset architectures, low-power design techniques, and performance-driven implementation. The candidate should be capable of owning IP/block-level development, resolving functional and timing issues, supporting verification and implementation activities, and ensuring delivery of robust, power-efficient, and high-performance designs for next-generation AI inference accelerators.

Key Responsibilities
✅ Define and implement hardware architectures optimized for AI inference SoCs
✅ Drive micro-architecture development and evaluate design trade-offs for complex SoCs
✅ Work on custom-ISA processors, high-speed interconnects, and high-bandwidth I/O designs

Required Skills
✔️ 9+ years of ASIC IP/SoC RTL Design experience
✔️Full-cycle ownership of IP design and implementation
✔️ Hands-on design experience with datapath and control architectures in CPU, GPU, DSP, DDR, and cache designs
✔️ Good understanding of synthesis, timing closure, and power analysis
✔️ Hands-on experience with Lint, CDC, and RDC methodologies
✔️ Strong debugging, problem-solving, and root-cause analysis skills
✔️ Experience working on complex SoC designs is highly preferred

📩 Interested candidates can share their resumes or connect for more details.
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