AS
ASIC Design and Development Engineer
Accepting applicationsAcara Solutions, An Aleron Company · Texas, United States, North America
Contract Senior ASICFPGAMentorRTLSoC
Posted
14 Apr
Category
Design
Experience
Senior
Country
United States
Acara is currently seeking a Senior ASIC Design and Development Engineer for our client, a leading organization in the defense and aerospace sector. This role offers an exciting opportunity to contribute to a dynamic team while developing your professional expertise. The ideal candidate will have experience in SoC/CPU/GPU architecture, AXI interconnects, high-speed interfaces, and high bandwidth techniques.
Job Title: Senior ASIC Design and Development Engineer
Location: On-Site - Dallas, TX
Employment Type: Contract (12 months)
Industry: Defense & Aerospace
Compensation: Up to $127/hr
Schedule: 9x80, 1st shift
What You'll Do:
- Lead FPGA design efforts across the full lifecycle-including simulation, synthesis, timing closure, verification, and system integration
- Design and develop advanced digital (and optical) hardware systems, ensuring performance, reliability, and manufacturability
- Translate customer requirements into innovative, cost-effective engineering solutions and system architectures
- Own technical execution-delivering projects on time and within budget while resolving complex engineering challenges
- Collaborate cross-functionally with manufacturing, supply chain, program management, and customers to drive successful outcomes
- Contribute to new business initiatives by developing technical concepts, supporting proposals, and engaging with customer design teams
- Mentor and support fellow engineers, providing technical guidance and fostering a high-performing team environment
What You'll Bring:
- Bachelor's degree in engineering or related technical field
- Minimum of 5 years of hands-on RTL design experience
- Minimum of 5 years of experience with Verilog / System Verilog
- Minimum of 5 years of experience with SoC/CPU/GPU architecture, AXI interconnects, high-speed interfaces, and high bandwidth techniques
- Minimum of 5 years of experience with design verification and functional coverage methodologies, including UVM