PC
ASIC Architect
Accepting applicationsPiper Companies · Saratoga, CA
Full-Time Mid_senior AIASICPCIeRTLSerDes
Posted
6d ago
Category
Design
Experience
Mid_senior
Country
United States
Piper Companies is hiring an ASIC Architect with a small start up based in Saratoga, CA. The ASIC Architect will drive the architectural definition of next-generation data center networking ASICs—shaping switch architectures, performance frameworks, and high-efficiency data paths tailored for AI training and inference. The ASIC Architect will need to sit on site in Saratoga, CA 5 days per week.
Responsibilities of the ASIC Architect:
Define architectures for high-performance networking ASICs
Translate system goals into scalable architecture plans
Drive queuing, memory, and scheduling strategies
Model and evaluate performance trade-offs
Collaborate across RTL, verification, and firmware teams
Oversee integration of high-speed I/O and memory interfaces
Support post-silicon bring-up and debug
Requirements for the ASIC Architect:
MSEE or equivalent with 10+ years in semiconductors; 5–7 years in ASIC architecture
Background in CPUs, GPUs, DPUs, or switches
Strong problem-solving and architecture methodology skills
Experience with queueing, memory, and scheduling in high-throughput systems
Familiar with scalable memory, crossbars, and high-speed datapaths
Bonus: knowledge of networking protocols
Excellent communication and documentation skills
Compensation for the ASIC Architect:
$270,000-$290,000
Comprehensive Benefits: Health, Vision, Dental, PTO, Paid Holiday, Sick Leave if Required by Law
Keywords: ASIC Architect, networking ASIC, switch architecture, system-level architecture, high-throughput systems, queueing, scheduling, memory management, high-speed datapaths, microarchitecture, performance modeling, interface integration, PCIe, SerDes, RTL collaboration, post-silicon validation, MSEE, AI infrastructure, semiconductor design, datapath architecture, parallel processing, hardware startup, AI data center, latency optimization, power efficiency, architectural trade-offs, cross-functional teams, hardware debugging, silicon bring-up, behavioral modeling
#ONSITE
This job opens for applications on 5/29/2026. Applications for this job will be accepted for at least 30 days from the posting date.
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Responsibilities of the ASIC Architect:
Define architectures for high-performance networking ASICs
Translate system goals into scalable architecture plans
Drive queuing, memory, and scheduling strategies
Model and evaluate performance trade-offs
Collaborate across RTL, verification, and firmware teams
Oversee integration of high-speed I/O and memory interfaces
Support post-silicon bring-up and debug
Requirements for the ASIC Architect:
MSEE or equivalent with 10+ years in semiconductors; 5–7 years in ASIC architecture
Background in CPUs, GPUs, DPUs, or switches
Strong problem-solving and architecture methodology skills
Experience with queueing, memory, and scheduling in high-throughput systems
Familiar with scalable memory, crossbars, and high-speed datapaths
Bonus: knowledge of networking protocols
Excellent communication and documentation skills
Compensation for the ASIC Architect:
$270,000-$290,000
Comprehensive Benefits: Health, Vision, Dental, PTO, Paid Holiday, Sick Leave if Required by Law
Keywords: ASIC Architect, networking ASIC, switch architecture, system-level architecture, high-throughput systems, queueing, scheduling, memory management, high-speed datapaths, microarchitecture, performance modeling, interface integration, PCIe, SerDes, RTL collaboration, post-silicon validation, MSEE, AI infrastructure, semiconductor design, datapath architecture, parallel processing, hardware startup, AI data center, latency optimization, power efficiency, architectural trade-offs, cross-functional teams, hardware debugging, silicon bring-up, behavioral modeling
#ONSITE
This job opens for applications on 5/29/2026. Applications for this job will be accepted for at least 30 days from the posting date.
Show more Show less