II
ASIC Architect
Accepting applicationsInterSources Inc · Saratoga, CA
Full-Time Executive ASICEthernetPCIeSerDesai
Posted
6d ago
Category
Design
Experience
Executive
Country
United States
MSEE with 10+ years of experience, preferably in networking ASIC architecture and design.
Candidates with experience in related areas of computer and parallel processing architectures – in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths – are also highly desired.
A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert.
Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Capability to develop Architecture behavioral models is highly desired.
Experience working across the ASIC development lifecycle, from concept through productization.
Experience in high-speed I/O integration (e.g., PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable.
Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power).
Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex issues. Exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly.
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Candidates with experience in related areas of computer and parallel processing architectures – in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths – are also highly desired.
A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert.
Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Capability to develop Architecture behavioral models is highly desired.
Experience working across the ASIC development lifecycle, from concept through productization.
Experience in high-speed I/O integration (e.g., PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable.
Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power).
Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex issues. Exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly.
Show more Show less