Application Specific Integrated Circuit Verification Engineer

Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause, and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality


Minimum Qualification
sB.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Scienc
eHands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodolog
yExperience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologie
sExperience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments
.Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycl

e
Preferred Qualificatio
nsExperience in the development of UVM based verification environments from scrat
chExperience with Design verification of Data-center applications like Video, AI/ML, and Networking desig
nsExperience with revision control systems like Mercurial(Hg), Git or S
VNExperience with verification of ARM/RISC-V based sub-systems or So

Cs
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