TT
Application Specific Integrated Circuit Verification Engineer
Accepting applicationsTara Technical Solutions (TTS) · San Jose, CA
Full-Time Mid_senior ASICEthernetSOCSoC
Posted
15 Jun
Category
Design
Experience
Mid_senior
Country
United States
H1B assistance and Canadian VISA support is available.
Boston or Santa Clara
Memory-to-Compute Fabric for LLM Data Centers.
Optimum verification methodology.
Artificial Intelligence/DataCenter space.
The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.
Excellent leadership..
Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
Outstanding technical expertise in verification methodologies.
Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.
Verification and tapeout of any advanced silicon device is highly preferred.
Post-Silicon validation of any silicon ASIC/SoC is highly preferred
Preferred Qualifications
PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience managing relationships with external design partners, IP vendors, and foundries.
Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.
Show more Show less
Boston or Santa Clara
Memory-to-Compute Fabric for LLM Data Centers.
Optimum verification methodology.
Artificial Intelligence/DataCenter space.
The work involves learning advanced LLM in modern data centers and applications to design memory acceleration.
Excellent leadership..
Strong knowledge across the full ASIC/SOC development cycle from microarchitecture development to tape-out in advanced process technologies.
Outstanding technical expertise in verification methodologies.
Hands-on design experience in one or more industry standards/protocol stacks such as Ethernet, UCIe, UALink etc.
Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory).
Proficiency with front-end development tools/methodologies, and scripting for automation and flow integration.
Verification and tapeout of any advanced silicon device is highly preferred.
Post-Silicon validation of any silicon ASIC/SoC is highly preferred
Preferred Qualifications
PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience managing relationships with external design partners, IP vendors, and foundries.
Knowledge of Design-For-Testability, post silicon debug/validation/manufacturing test.
Show more Show less
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