MA
Application Specific Integrated Circuit Verification Engineer
Accepting applicationsMobile Apps US · Sunnyvale, CA
Full-Time Mid_senior ASICSoCSystemVerilogUVM
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
ASIC Verification Engineer
Location: Sunnyvale, CA – Hybrid (2 days/week onsite)
Visa: Non-visa holders preferred; H1B transfers considered
Start: ASAP
Job Summary
Seeking an experienced ASIC Verification Engineer to drive block, subsystem, and full-chip verification for complex networking ASIC/SoC designs.
Key Requirements
5+ years of ASIC/SoC verification experience.
Strong SystemVerilog and UVM expertise; ability to build verification environments from scratch.
Experience with test planning, constrained-random testing, coverage closure, functional coverage, and SVA assertions.
Hands-on debugging of complex SoC designs using Xcelium, VCS, or Questa and waveform analysis.
Experience developing UVM components such as agents, sequences, scoreboards, virtual sequences, and register models.
Preferred
Networking ASIC/SoC or router datapath/control block verification.
Knowledge of packet processing, forwarding engines, fabric interfaces, high-speed interconnects, or scheduling pipelines.
Experience with emulation, post-silicon debug, UPF/low-power, formal verification, Jenkins/CI, and regression/coverage analytics.
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Location: Sunnyvale, CA – Hybrid (2 days/week onsite)
Visa: Non-visa holders preferred; H1B transfers considered
Start: ASAP
Job Summary
Seeking an experienced ASIC Verification Engineer to drive block, subsystem, and full-chip verification for complex networking ASIC/SoC designs.
Key Requirements
5+ years of ASIC/SoC verification experience.
Strong SystemVerilog and UVM expertise; ability to build verification environments from scratch.
Experience with test planning, constrained-random testing, coverage closure, functional coverage, and SVA assertions.
Hands-on debugging of complex SoC designs using Xcelium, VCS, or Questa and waveform analysis.
Experience developing UVM components such as agents, sequences, scoreboards, virtual sequences, and register models.
Preferred
Networking ASIC/SoC or router datapath/control block verification.
Knowledge of packet processing, forwarding engines, fabric interfaces, high-speed interconnects, or scheduling pipelines.
Experience with emulation, post-silicon debug, UPF/low-power, formal verification, Jenkins/CI, and regression/coverage analytics.
Show more Show less