M
Application Specific Integrated Circuit Engineer
Accepting applicationsMaximaTek · California, United States
Full-Time Entry ASICCMOSCadenceDFTFPGA
Posted
4d ago
Category
Design
Experience
Entry
Country
United States
🚀 Hiring: VLSI Design Engineer (Entry Level / Junior) – Remote | USA
📍 Location: California (United States)
💼 Job Type: Full-Time
📈 Experience: 0–3 Years
🛂 Visa Status: We welcome candidates with F-1 OPT, STEM.
We are seeking a motivated VLSI Design Engineer to join our growing semiconductor engineering team. This is an excellent opportunity for recent graduates and early-career professionals who are passionate about ASIC/FPGA Design, RTL Development, and Digital IC Design.
Key Responsibilities
Design, develop, and verify digital circuits for ASIC and FPGA applications.
Develop RTL using Verilog/SystemVerilog.
Perform simulation, debugging, and functional verification.
Support synthesis, timing analysis, and design optimization.
Collaborate with cross-functional engineering teams to deliver high-quality designs.
Prepare technical documentation and resolve design issues.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
0–3 years of experience in VLSI Design, ASIC, FPGA, or Digital Design.
Strong understanding of Digital Logic Design, CMOS Fundamentals, RTL Design, and Verilog/SystemVerilog.
Familiarity with ASIC/FPGA design flow.
Excellent analytical, problem-solving, and communication skills.
Preferred Skills
Experience with Cadence, Synopsys, Mentor Graphics, or Xilinx Vivado.
Knowledge of Python, TCL, or Perl scripting.
Understanding of STA, DFT, UVM, and Linux/Unix is a plus.
📩 Interested candidates, please share your updated resume : pravalika.b@maximatek.com
#Hiring #NowHiring #RemoteJobs #RemoteWork #FullTimeJobs #VLSI #VLSIDesign #ASIC #FPGA #RTLDesign #Verilog #SystemVerilog #DigitalDesign #Semiconductor #ChipDesign #ICDesign #EDA #Cadence #Synopsys #Xilinx #ElectronicsEngineering #ElectricalEngineering #ComputerEngineering #EngineeringJobs #TechJobs #USJobs #OPT #STEMOPT #F1OPT #F1Students #EntryLevelJobs #CareerOpportunity #HiringNow
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📍 Location: California (United States)
💼 Job Type: Full-Time
📈 Experience: 0–3 Years
🛂 Visa Status: We welcome candidates with F-1 OPT, STEM.
We are seeking a motivated VLSI Design Engineer to join our growing semiconductor engineering team. This is an excellent opportunity for recent graduates and early-career professionals who are passionate about ASIC/FPGA Design, RTL Development, and Digital IC Design.
Key Responsibilities
Design, develop, and verify digital circuits for ASIC and FPGA applications.
Develop RTL using Verilog/SystemVerilog.
Perform simulation, debugging, and functional verification.
Support synthesis, timing analysis, and design optimization.
Collaborate with cross-functional engineering teams to deliver high-quality designs.
Prepare technical documentation and resolve design issues.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
0–3 years of experience in VLSI Design, ASIC, FPGA, or Digital Design.
Strong understanding of Digital Logic Design, CMOS Fundamentals, RTL Design, and Verilog/SystemVerilog.
Familiarity with ASIC/FPGA design flow.
Excellent analytical, problem-solving, and communication skills.
Preferred Skills
Experience with Cadence, Synopsys, Mentor Graphics, or Xilinx Vivado.
Knowledge of Python, TCL, or Perl scripting.
Understanding of STA, DFT, UVM, and Linux/Unix is a plus.
📩 Interested candidates, please share your updated resume : pravalika.b@maximatek.com
#Hiring #NowHiring #RemoteJobs #RemoteWork #FullTimeJobs #VLSI #VLSIDesign #ASIC #FPGA #RTLDesign #Verilog #SystemVerilog #DigitalDesign #Semiconductor #ChipDesign #ICDesign #EDA #Cadence #Synopsys #Xilinx #ElectronicsEngineering #ElectricalEngineering #ComputerEngineering #EngineeringJobs #TechJobs #USJobs #OPT #STEMOPT #F1OPT #F1Students #EntryLevelJobs #CareerOpportunity #HiringNow
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