Application Specific Integrated Circuit Design Engineer

Role: RTL Design Tech Lead (ASIC/SoC)
Type: Full Time
Location: Sunnyvale, CA

About the Company

Client is a semiconductor startup based in Sunnyvale, CA building the fastest and most efficient graphics processors. We pride ourselves on our first principles approach to solving problems. We are energized by our mission to reduce the barrier of entry for content creation and consumption. Our goal is to enable everyone to easily create, simulate and consume immersive experiences as vividly as they can imagine them.


Our Values

Be Fearless: Unmute yourself. Test boundaries and get proven right.
Remain Adaptable: Stay comfortable in a continuously changing world. If you’re wrong, concede and move on.
Educate Your Ego: Selflessly collaborate towards our shared purpose.


About the Role
We're looking for a seasoned RTL Design Tech Lead to drive micro-architecture, RTL development, and technical execution for complex ASIC/SoC programs. This role combines deep hands-on design expertise with technical leadership, guiding teams from architecture through tapeout. The ideal candidate has strong ownership mindset, has led successful silicon bring-ups, and can operate effectively in both structured and fast-paced environments. This candidate must be willing to be an individual contributor, while leading others. This is an on-site role and will require presence in the office 5 days a week. No hybrid option is available.


Responsibilities
Drive micro-architecture and RTL development.
Guide teams from architecture through tapeout.
Lead successful silicon bring-ups.
Operate effectively in both structured and fast-paced environments.
Be an individual contributor while leading others.

Qualifications
Bachelor’s or Master’s in Electrical / Computer Engineering.
10+ years of experience in ASIC/SoC RTL design.


Required Skills
Expert-level proficiency in:
SystemVerilog / Verilog RTL coding.
Micro-architecture design.
Strong understanding of:
Timing (setup/hold, STA correlation).
CDC/RDC methodologies.
Reset strategies and clocking architectures.
Low-power design (UPF/CPF).
Proven experience leading blocks through multiple tapeouts.
Hands-on experience with synthesis (e.g., Design Compiler).
Strong debugging and problem-solving ability.
Excellent communication across cross-functional teams.
Ownership and accountability for silicon success.
Ability to operate under tight tapeout schedules.

Must have Any -4 from below Qualifications:
Experience in advanced nodes (e.g., 12FFC, 7nm, 5nm).
Strong GLS expertise (SDF, X-propagation, power-aware sims).
Knowledge of DFT (scan, MBIST, compression).
Experience with high-speed IPs (DDR, PCIe, SerDes) or memory subsystems.
Scripting proficiency (Python / Tcl).
Prior collaboration with foundries such as TSMC.
Experience in startup environments or first-silicon efforts.
Exposure to packaging (flip-chip, bump planning, IO constraints).
Experience with low-frequency testchips or rapid prototyping.
Government clearance is preferred.


Leadership Expectations

As an IC, you will provide technical direction and architectural clarity.
Mentor and grow team members.
Drive high engineering standards and design quality.
Influence cross-functional decisions.
Balance hands-on work with leadership responsibilities.



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