Application Specific Integrated Circuit Design Engineer

Position Name: ASIC RTL Design Engineer
Experience: 5+ Years
Location: Bangalore / Pune
Job Summary
We are seeking an experienced ASIC RTL Design Engineer with strong expertise in digital design, Verilog coding, RTL integration, synthesis, and timing closure. The ideal candidate should have hands-on experience in ASIC/SoC design flow and a strong understanding of digital design fundamentals.
Key Responsibilities
• Develop and maintain high-quality RTL designs using Verilog.
• Perform RTL integration for complex ASIC/SoC designs.
• Collaborate with Architecture, Verification, Physical Design, and DFT teams.
• Analyze and resolve RTL design issues during development and integration.
• Support synthesis and timing closure activities.
• Debug and fix timing violations, including setup and hold issues.
• Participate in design reviews and ensure compliance with design specifications.
• Work closely with cross-functional teams to achieve project milestones.
Required Skills
• Minimum 5+ years of experience in ASIC RTL Design.
• Strong hands-on experience in Verilog coding.
• Experience in RTL design and RTL integration.
• Good understanding of digital design concepts and computer architecture fundamentals.
• Experience with synthesis tools such as Synopsys Design Compiler or Cadence Genus.
• Strong knowledge of Static Timing Analysis (STA).
• Experience in timing closure and timing violation fixes.
• Understanding of ASIC design and development flow.
Technical Expertise
• Verilog HDL
• RTL Design and Development
• RTL Integration
• ASIC/SoC Design
• Synthesis
• Static Timing Analysis (STA)
• Timing Closure
• Setup and Hold Violation Analysis
• Digital Logic Design

Desired Candidate Profile
• Strong analytical and debugging skills.
• Good communication and teamwork abilities.
• Ability to independently drive design tasks and deliver high-quality solutions.
• Experience working in complex ASIC/SoC development environments.

Strong Match
• 5+ years ASIC RTL Design experience.
• Strong Verilog coding expertise.
• Hands-on RTL integration experience.
• Synthesis and STA exposure.
• Timing closure and violation-fix experience.
• Good digital design fundamentals.
Reject
• FPGA-only profiles.
• Verification/UVM-only profiles.
• DFT-only profiles.
• Physical Design-only profiles.
• Candidates without RTL coding experience.
• Candidates without synthesis/timing knowledge.
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