Application Specific Integrated Circuit Design Engineer

Two Requirements :
Requirement 1: Design Verification Engineer
Requirement 2: Design Engineer
Let me know which requirement works for you: 1 or 2?

Requirement 1: Design Verification Engineer

Role: Design Verification Engineer
Location: San Jose CA/ Irvine, CA / San Diego, CA - onsite
Salary: $220K base + full-time benefits

Job Description:
Experience: 6 to 15+ years of experience.
Job Requirements are as below:
Architect block and full-chip verification environments using HVLs and constrained random
techniques for SOCs with embedded CPUs and mixed-signal interfaces. Requires UVM, System Verilog, SVA
○ Develop test plans and coverage metrics from specifications and write block and chip-level
tests in C, SV, UVM
○ Debug RTL and Gate simulations and work with design engineers to verify fixes.
○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC.
○ Replicate silicon bugs in simulation environments and validate fixes or SW workarounds.
○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup.
○ Evaluate latest verification methodologies and develop scripts, etc. to automate verification
flows.

Requirement 2: Physical Design Engineer

Physical Design Engineer
No of positions: 2
Locations: Austin, TX and San Jose, CA
Salary: $180K -$ 200 K + Benefits
H1B transfer ok
Relocation ok

Job Details:

Skills And Qualifications

11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
7+ years of hands-on experience with ASIC design flows and electrical engineering fundamentals.
Strong experience with POCV, derating methodologies, and timing analysis.
Strong hands-on experience with industry-standard STA tools (e.g., PrimeTime, Tempus), clock tree synthesis (CTS), multi-voltage and multi-clock designs.
Strong knowledge of formal equivalency checks, low-power checks, timing constraints, UPF.
Strong scripting /programming skills in Tcl, Perl, Shell, and/or Python.
Strong analytical skills, attention to detail, and problem-solving skills using a data-driven approach.
Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers
Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.

Nice to have:

Familiarity with advanced FinFET process nodes (5nm or smaller).
Hands-on experience with synthesis, block and/or full chip implementation with the latest industry P&R/STA flows and tools.
Sign-off experience with reliability, signal integrity, noise, timing, and power
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