Application Specific Integrated Circuit Design Engineer

Member of Technical Staff – ASIC Design – Santa Clara, CA / Boston, MA (Onsite)

I'm currently hiring for an early-stage AI infrastructure company building a new memory layer for modern AI systems. They're developing custom silicon that gives GPUs and other accelerators access to a much larger, high-bandwidth memory tier, helping solve the growing memory capacity and data-movement bottlenecks created by long-context inference, agentic workloads and KV-cache-heavy applications.

The company is building across ASIC architecture, RTL, networking, memory systems and ML infrastructure, with the hardware and software teams working closely together from first principles. They're now looking for experienced ASIC Designers who can take ownership across microarchitecture, RTL design and silicon execution. This is an opportunity to have a major influence on an early silicon roadmap, working on IPs, subsystems and SoCs designed specifically for next-generation AI and high-performance computing workloads.

What they're looking for:
Strong experience with microarchitecture development and RTL design using Verilog / SystemVerilog
Knowledge across the ASIC development lifecycle, including synthesis, STA / timing closure, physical design and verification
Experience designing or integrating interconnect, I/O or memory subsystems
Hands-on experience with protocols such as Ethernet, UCIe, UALink or similar
Experience taking advanced silicon through tape-out is highly preferred

Important details:
Fully onsite in Santa Clara, CA or Boston, MA
Up to $275K base + performance bonus + early-stage equity
Relocation assistance and visa sponsorship available

Be sure to apply to find out more!
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