Analog/Mixed-Signal Verification Engineer

Responsibilities

Develop and implement mixed-signal verification and coverage plans for complex IC designs based on design architecture and specifications
Design and develop verification testbenches using industry-standard verification languages and methodologies
Write and execute test cases to verify mixed-signal circuits for functionality, performance, and reliability
Review and analyze verification results, and provide feedback to design teams
Collaborate with design and layout teams to identify and resolve design issues
Develop new verification methodologies, tools, and techniques, ensuring scalability and portability
Sign-off mixed signal designs in preparation for tapeout
Write behavioral models from custom analog and mixed-signal circuits in SystemVerilog HDL
Collaborate with circuit design teams to understand fine details of custom circuits
Collaborate with Design Verification team to craft hooks into the behavioral models for effective verification
Run various simulations and equivalence checks to ensure that the model matches closely with the custom circuits
Write scripts and simple tools for automating repetitive tasks
Optimize and refine models to ensure accuracy while maintaining efficient simulation performance
Review and analyze verification results, and provide feedback to design team
Document modeling techniques and results for internal and external dissemination
Keep updated with industry trends in modeling techniques

Requirements

Bachelor's degree in Electrical Engineering and 5+ years of relevant industry experience or equivalent
Strong understanding of analog and mixed-signal circuit design and verification principles
Ability to write test plans, present results, and communicate clearly with multi-functional teams
Have a familiarity with verification methodologies and tools: simulators, waveform viewers, execution automation, simulation time optimization, and coverage collection
Familiarity with analog behavioral models is a plus
Deep knowledge of Verilog/SystemVerilog with ability to write synthesize-able and behavioral code
Deep knowledge of digital logic gates, clocking and state elements
Deep knowledge of SPICE simulation, HDL simulation and logic equivalence tools
Working understanding of analog circuit architecture such as ADC, DAC, LDO, Charge pump, etc.
Have good programming skills and can write efficient programs or scripts in Perl, Python, and/or C
Excellent debugging, problem-solving and analytical skills
Strong communication and teamwork skills

Salary Range: $110,000 - $300,000 / year

TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.

TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.

To ensure a fair, consistent, and efficient hiring process, all candidates must apply through TetraMem’s official ClearCompany Applicant Tracking System (ATS). Applications submitted through the ATS allow our hiring team to evaluate candidates using a standardized process and ensure timely communication throughout the recruitment process. To promote equal consideration for all applicants, applications submitted outside of the ClearCompany ATS, including direct emails, LinkedIn messages, or unsolicited submissions to employees, may not be reviewed or considered.

We encourage all interested candidates to apply through the official TetraMem Careers page.
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