Analog Mixed Signal Validation and Verification

Hiring: Analog Mixed Signal (AMS) Validation & Verification Engineer
📍 Location: Bangalore (Onsite)
Key Skills Required
AMS Verification
AXUM / AVUM
UVM-AMS
SystemVerilog
UVM
Verilog-A / Verilog-AMS
SV-RNM
SPICE Simulation
Mixed Signal Verification
Cadence Virtuoso
Synopsys VCS
Xcelium
Analog & Digital Design Concepts
PERL / TCL / Python Scripting
Roles & Responsibilities
Develop AMS simulation methodologies and verification flows (AXUM, AVUM, UVM-AMS).
Create and execute verification plans for AMS SoCs, IPs, and subsystems.
Run, debug, and analyze SPICE-based and digital simulations.
Develop behavioral models using Verilog-A/AMS, SV-RNM, and VHDL-AMS.
Collaborate with Analog, Digital, and RTL teams to track design updates.
Review simulation setups and validate test conditions.
Automate verification workflows using scripting languages.
Document verification findings, debug reports, and methodology improvements.
Mentor team members and contribute to technical discussions and debugging sessions.
Preferred Experience
Strong expertise in AMS verification methodologies.
Hands-on experience with Cadence and Synopsys verification tools.
Deep understanding of Analog and Digital design fundamentals.
Experience with assertion-based verification and behavioral modeling.
Strong debugging and problem-solving skills.
📩 If Interested, please share your updated CV:
Email: Khushboo@Sourcebae.com
WhatsApp: +91 88275 65832
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