SS
Analog Mixed Signal Layout Engineer
Accepting applicationsSILCOSYS Solutions Pvt. Ltd. · Hyderabad, Telangana, India
Full-Time Entry AnalogCadenceCalibreMixed Signalanalog
Estimated market salary
₹10-18 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
2d ago
Category
Design
Experience
Entry
Country
India
Role Overview
We are looking for an experienced Analog Mixed Signal Layout Engineer with strong hands-on expertise in custom analog/digital layout design and verification. The ideal candidate should have 5–7 years of practical experience in independent block/module layouts using Cadence layout design tools, along with mandatory experience in TSMC 5nm or lower technology nodes.
Technical Expertise
5–7 years of hands-on experience in independent block/module layouts using Cadence Layout design tools.
Mandatory experience with TSMC 5nm or lower technology nodes.
Experience in TSMC 3nm and below for custom analog/digital block layouts.
Strong knowledge of Cadence Virtuoso EXL/GXL, Calibre, and other layout design and verification tools.
Experience developing custom layouts for high-speed analog/digital blocks such as Ring Oscillators, Dividers, Bias Blocks, Voltage & Current References, and pre-drivers.
Key Responsibilities
Develop custom layouts for high-speed analog and digital blocks in TSMC 3nm and below.
Independently debug and resolve layout issues across various verification flows.
Take up different tasks based on project requirements and priorities.
Own and manage assigned blocks and larger macros with complete accountability.
Execute release flows and drive layouts to closure within defined milestones and timelines.
Identify potential issues in advance and raise concerns proactively.
Collaborate with the team on block-level specifications to ensure effective integration of top modules.
Create and review all relevant layout design views using sign-off tools and established flows.
Deliverables
Complete layout designs meeting the required quality standards.
All specified verification flows clean and ready for sign-off.
Relevant layout design views created and checked using sign-off tools and flows.
Required documentation completed as per project requirements.
Qualification
B.E./B.Tech/M.E./M.Tech/MS in Electrical Engineering.
Experience
5–10 years of relevant industry experience.
5–7 years of hands-on experience in block/module layouts using Cadence Layout design tools.
Mandatory experience with TSMC 5nm or lower technology nodes.
Strong proficiency in Cadence Virtuoso EXL/GXL, Calibre, and related layout verification tools.
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We are looking for an experienced Analog Mixed Signal Layout Engineer with strong hands-on expertise in custom analog/digital layout design and verification. The ideal candidate should have 5–7 years of practical experience in independent block/module layouts using Cadence layout design tools, along with mandatory experience in TSMC 5nm or lower technology nodes.
Technical Expertise
5–7 years of hands-on experience in independent block/module layouts using Cadence Layout design tools.
Mandatory experience with TSMC 5nm or lower technology nodes.
Experience in TSMC 3nm and below for custom analog/digital block layouts.
Strong knowledge of Cadence Virtuoso EXL/GXL, Calibre, and other layout design and verification tools.
Experience developing custom layouts for high-speed analog/digital blocks such as Ring Oscillators, Dividers, Bias Blocks, Voltage & Current References, and pre-drivers.
Key Responsibilities
Develop custom layouts for high-speed analog and digital blocks in TSMC 3nm and below.
Independently debug and resolve layout issues across various verification flows.
Take up different tasks based on project requirements and priorities.
Own and manage assigned blocks and larger macros with complete accountability.
Execute release flows and drive layouts to closure within defined milestones and timelines.
Identify potential issues in advance and raise concerns proactively.
Collaborate with the team on block-level specifications to ensure effective integration of top modules.
Create and review all relevant layout design views using sign-off tools and established flows.
Deliverables
Complete layout designs meeting the required quality standards.
All specified verification flows clean and ready for sign-off.
Relevant layout design views created and checked using sign-off tools and flows.
Required documentation completed as per project requirements.
Qualification
B.E./B.Tech/M.E./M.Tech/MS in Electrical Engineering.
Experience
5–10 years of relevant industry experience.
5–7 years of hands-on experience in block/module layouts using Cadence Layout design tools.
Mandatory experience with TSMC 5nm or lower technology nodes.
Strong proficiency in Cadence Virtuoso EXL/GXL, Calibre, and related layout verification tools.
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