Analog Layout Engineer

Company Description SiMaxTech Pvt Ltd is a fast-growing semiconductor design services company that delivers end-to-end chip solutions for global customers. The team supports the full semiconductor design spectrum, including analog circuit design, custom layout, RTL, verification, physical design, embedded design, and SoC backend. With experience from mature nodes like 65nm and 40nm to advanced technologies such as 7nm, 5nm, 3nm, and emerging nodes like 2nm and 18A, SiMaxTech is positioned at the forefront of next-generation product development. The company emphasizes continuous learning, innovation, and execution excellence to provide high-performance, reliable, and scalable solutions. Its mission is to be the preferred semiconductor design services partner, supporting customers across the entire chip development lifecycle.

We're Hiring,
Lead Analog Layout Engineers
Experience: 6-10
Location: Bangalore
Notice Period: Immediate - 30 Days

Role Description This is a full-time, on-site Analog Layout Engineer role based in Bengaluru South. The Analog Layout Engineer will be responsible for custom layout implementation of analog and mixed-signal blocks, including transistor-level schematics, floorplanning, device matching, and parasitic-aware layout. The role involves working closely with circuit design engineers to understand specifications, optimize layouts for performance, area, reliability, and manufacturability, and perform layout verification using DRC, LVS, ERC, and related checks. The engineer will prepare and maintain layout documentation, review sign-off reports, and support tape-out activities across multiple process nodes. Collaboration with cross-functional teams and adherence to project schedules, quality standards, and design guidelines are key aspects of the day-to-day work.
Qualifications
Strong expertise in analog and mixed-signal layout for blocks such as amplifiers, comparators, data converters, bias circuits, and IO structures.
Hands-on experience with industry-standard layout and verification tools (e.g., Cadence Virtuoso, Mentor/Siemens Calibre, Synopsys tools or equivalents) for DRC, LVS, and parasitic extraction.
Solid understanding of CMOS device physics, matching techniques, common-centroid and interdigitated layout practices, and layout-dependent effects.
Familiarity with advanced process nodes (e.g., 28nm and below) and related design considerations such as EM/IR, ESD, and reliability constraints.
Ability to interpret schematics, constraints, and design guidelines, and translate them into robust, manufacturable layouts.
Good knowledge of full-custom layout methodologies, floorplanning, power routing, shielding, and noise-sensitive layout practices.
Effective communication and teamwork skills to collaborate with circuit design, verification, and physical design teams.
Strong attention to detail, quality-focused mindset, and ability to manage multiple tasks and deadlines.
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