AS
Analog Layout Engineer
Accepting applicationsAcme Services · Bengaluru, Karnataka, India
Full-Time Mid_senior AnalogCadenceCalibreMixed-SignalRF
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
India
Hiring experienced Analog Layout Engineer - Leading Global semiconductor Design Organization
Experience: 4 to 12 Years
Location: Hyderabad & Bangalore
We are looking for experienced Analog Layout Engineers to work on next-generation Analog, Mixed-Signal, and RF IC designs. This role offers the opportunity to work on advanced semiconductor technologies, lead custom layout activities, and collaborate with global engineering teams to deliver high-performance silicon solutions.
Key Responsibilities:
Hands-on experience in Custom Analog Layout for blocks such as PLL, DLL, LNA, VGA, ADC, DAC, LDO, Bandgap, VCO, and RF Transceivers.
Strong expertise in Cadence Virtuoso/Virtuoso XL, SKILL Programming, and physical verification tools such as Calibre, Assura, and Hercules.
Experience in PCell development, PDK maintenance, and custom layout methodologies.
Strong understanding of physical verification (DRC/LVS/ERC), semiconductor process technologies, and fabrication concepts.
Ability to lead and mentor a team of layout engineers while acting as the technical focal point for customers.
Good understanding of analog design concepts with exposure to digital Place & Route being an added advantage.
Interested candidates can share their resume at: kinjal@acme-services.in
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Experience: 4 to 12 Years
Location: Hyderabad & Bangalore
We are looking for experienced Analog Layout Engineers to work on next-generation Analog, Mixed-Signal, and RF IC designs. This role offers the opportunity to work on advanced semiconductor technologies, lead custom layout activities, and collaborate with global engineering teams to deliver high-performance silicon solutions.
Key Responsibilities:
Hands-on experience in Custom Analog Layout for blocks such as PLL, DLL, LNA, VGA, ADC, DAC, LDO, Bandgap, VCO, and RF Transceivers.
Strong expertise in Cadence Virtuoso/Virtuoso XL, SKILL Programming, and physical verification tools such as Calibre, Assura, and Hercules.
Experience in PCell development, PDK maintenance, and custom layout methodologies.
Strong understanding of physical verification (DRC/LVS/ERC), semiconductor process technologies, and fabrication concepts.
Ability to lead and mentor a team of layout engineers while acting as the technical focal point for customers.
Good understanding of analog design concepts with exposure to digital Place & Route being an added advantage.
Interested candidates can share their resume at: kinjal@acme-services.in
Show more Show less