AD
Analog Layout Engineer
Accepting applicationsACL Digital · Bangalore Urban, Karnataka, India
Full-Time Mid_senior AnalogCadenceMixed-Signalaianalog
Posted
5d ago
Category
Design
Experience
Mid_senior
Country
India
Position: Analog Layout Engineer
Location: Hyderabad, India
Experience: 3+ Years
Job Requirements:
3+ years of experience in Analog/Mixed-Signal Layout Design.
Strong hands-on experience with TSMC process nodes (mandatory).
Expertise in layout of analog blocks such as:
Current Mirrors
Differential Pairs
Amplifiers
Bandgap References
LDOs
ADC/DAC-related circuits
Good understanding of:
Device matching techniques
Common-centroid layout
Interdigitation
Parasitic effects
ESD and latch-up considerations
Experience with DRC, LVS, ERC, and physical verification sign-off flows.
Proficiency in layout tools such as Cadence Virtuoso.
Ability to work closely with circuit designers and support post-layout verification activities.
Familiarity with advanced TSMC nodes is highly preferred.
Responsibilities:
Develop and verify high-quality analog and mixed-signal layouts.
Ensure layout compliance with foundry and design guidelines.
Perform DRC/LVS/ERC closure and support tape-out activities.
Collaborate with design, verification, and methodology teams to meet project schedules.
Mandatory Skill:
Hands-on experience in TSMC technology nodes.
If you're planning to post this for hiring, I can also make it recruiter-ready with preferred nodes (e.g., TSMC 28nm/16nm/12nm/7nm) and specific analog IP requirements.
Interested please share your resume to anusha.prakash@acldigital.com
Show more Show less
Location: Hyderabad, India
Experience: 3+ Years
Job Requirements:
3+ years of experience in Analog/Mixed-Signal Layout Design.
Strong hands-on experience with TSMC process nodes (mandatory).
Expertise in layout of analog blocks such as:
Current Mirrors
Differential Pairs
Amplifiers
Bandgap References
LDOs
ADC/DAC-related circuits
Good understanding of:
Device matching techniques
Common-centroid layout
Interdigitation
Parasitic effects
ESD and latch-up considerations
Experience with DRC, LVS, ERC, and physical verification sign-off flows.
Proficiency in layout tools such as Cadence Virtuoso.
Ability to work closely with circuit designers and support post-layout verification activities.
Familiarity with advanced TSMC nodes is highly preferred.
Responsibilities:
Develop and verify high-quality analog and mixed-signal layouts.
Ensure layout compliance with foundry and design guidelines.
Perform DRC/LVS/ERC closure and support tape-out activities.
Collaborate with design, verification, and methodology teams to meet project schedules.
Mandatory Skill:
Hands-on experience in TSMC technology nodes.
If you're planning to post this for hiring, I can also make it recruiter-ready with preferred nodes (e.g., TSMC 28nm/16nm/12nm/7nm) and specific analog IP requirements.
Interested please share your resume to anusha.prakash@acldigital.com
Show more Show less