Analog High-Speed I/O Design Engineer – SerDes / DDR / HCSL

Job Title: Analog High-Speed I/O Design Engineer – SerDes / DDR / HCSL
Location: Sanjose, CA
Experience: 8+ Years

Role Summary
Responsible for the architecture, transistor-level design, simulation, verification, and silicon validation of high-speed analog I/O circuits for advanced SoCs, ASICs, networking, storage, and compute applications. The primary focus is high-speed interface design including SerDes, DDR, HCSL, differential I/O, clocking, and high-speed receiver/transmitter circuits.
Primary Responsibilities
Design and develop high-speed analog/mixed-signal I/O circuits from architecture through silicon validation.
Own transistor-level design of:
SerDes TX/RX analog front ends
TX drivers and RX input stages
Differential amplifiers, limiting amplifiers, and comparators
CTLE/DFE-related analog blocks where applicable
Clock/data recovery interface circuits
High-speed PLL/DLL and clock distribution interface circuits
DDR PHY analog I/O circuits
DDR output drivers, receivers, termination and calibration circuits
HCSL/clock output drivers and receivers
Differential and single-ended high-speed I/O buffers
ESD-aware I/O structures and pad interfaces
Develop architectures addressing speed, jitter, power, noise, area, linearity, and PVT robustness.
Perform transistor-level simulations including:
DC/AC/transient
PVT and Monte Carlo
Mismatch and statistical analysis
Corner simulations
Noise and jitter analysis
Eye diagrams and BER-related analysis
Analyze and optimize signal integrity, including:
Impedance matching
Reflections
Crosstalk
ISI
Jitter
Duty-cycle distortion
Simultaneous switching noise
Package/channel effects
Work closely with digital, physical design, package, ESD, SI/PI, and system teams to achieve interface specifications.
Participate in IBIS/SPICE/channel modeling and high-speed link simulations.
Define and verify electrical specifications such as:
Data rate
Output swing
Common-mode range
Input sensitivity
Rise/fall time
Output impedance
Jitter
Eye opening
BER
Power consumption
Support layout implementation, including floorplanning, matching, shielding, sensitive-node isolation, routing, and parasitic-aware design.
Perform post-layout extraction and simulation and resolve performance degradation caused by parasitics.
Develop silicon evaluation plans and debug ATE/lab characterization results.
Correlate pre-silicon simulations with silicon measurements and drive design improvements.
Contribute to design reviews, technical documentation, IP specifications, and design methodology improvements.
Required Technical Skills
Primary — High-Speed Analog I/O
Strong hands-on experience in analog high-speed I/O circuit design.
Deep understanding of high-speed differential signaling and transmission-line behavior.
Strong transistor-level CMOS design skills.
Experience with high-speed drivers, receivers, termination, equalization, and clocking circuits.
SerDes
Practical experience with SerDes TX/RX design.
Understanding of:
NRZ/PAM signaling
TX/RX equalization
CTLE
DFE
CDR concepts
Jitter
Eye/BER analysis
Channel loss and ISI
Differential signaling
Experience with multi-Gbps interfaces is highly desirable.
DDR
Strong understanding of DDR PHY analog I/O.
Experience with DDR drivers/receivers, termination, impedance calibration, DQS/DQ interfaces, and training/calibration concepts.
Knowledge of DDR3/DDR4/DDR5 or LPDDR interfaces is preferred.
HCSL
Strong understanding of HCSL electrical specifications and differential clock I/O design.
Experience designing HCSL/current-steering output drivers, receivers, termination, and clock interfaces.
Understanding of common-mode, output swing, edge-rate, impedance, and jitter requirements.
Design & Verification Tools
Experience with tools such as:
Cadence Virtuoso / Spectre
HSPICE or equivalent SPICE simulators
MATLAB/Python for data analysis and modeling
Cadence ADE / Ocean / SKILL
High-speed channel/SI simulation tools such as Keysight ADS, Ansys HFSS, or equivalent
Extraction tools such as Quantus/Calibre
Waveform and eye-diagram analysis
Lab equipment such as high-bandwidth oscilloscopes, BERTs, VNAs, and high-speed probes
Preferred Qualifications

B.Tech/M.Tech/M.S./Ph.D. in Electrical/Electronics Engineering.
Typically 5–15+ years of relevant experience, depending on level.
Proven silicon experience in high-speed analog/mixed-signal I/O.
Experience in advanced CMOS processes and low-voltage design.
Experience taking IP from architecture → schematic → layout → extraction → tapeout → silicon bring-up.
Strong understanding of device physics, analog circuit fundamentals, parasitic effects, and process variation.
Experience with advanced-node challenges such as reduced voltage headroom, increased parasitics, leakage, and supply noise.

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