MC

Analog Design Engineer

Accepting applications

MRL Consulting Group | Global Niche Technology Recruitment · San Jose, United States, North America

Full-Time Senior AnalogCMOSCadenceGaNRF
Posted
10 Apr
Category
Design
Experience
Senior
Country
United States

RFIC / Analog IC Design Engineer – Bay Area (Hybrid)

We’re working with a well-funded, venture-backed semiconductor start-up in the Bay Area developing next-generation high-speed connectivity and optical interconnect technology.

They are looking for a hands-on RFIC / Analog IC Designer to play a key role in the design of cutting-edge high-frequency and high-speed analog blocks.

🚀 The Opportunity

You’ll join a small, high-calibre design team tackling challenging problems at the intersection of RF, mmWave, and optical connectivity. This is a highly visible role with real ownership and impact on architecture, design, and silicon success.

🔧 What You’ll Be Doing

  • Design and develop RF / analog / mixed-signal IC blocks such as:
  • TIAs
  • drivers
  • amplifiers (LNA, VGA)
  • PLL/CDR or high-speed interface circuits
  • Work across the full design cycle: spec → architecture → schematic → simulation → silicon validation
  • Collaborate closely with layout on parasitic-aware design and performance closure
  • Run and interpret pre- and post-layout simulations, including PVT and Monte Carlo
  • Contribute to first-pass silicon success in a fast-moving tape-out environment

✅ What We’re Looking For

  • 5+ years of experience in RFIC / analog IC design
  • Strong fundamentals in analog and RF circuit design
  • Experience with Cadence (Virtuoso, Spectre) or similar tools
  • Background in one or more:
  • SiGe BiCMOS / high-speed CMOS
  • GaAs / GaN / InP
  • Experience designing circuits operating at high frequencies (>20 GHz) or high data rates (50G–200G+)

⭐ Nice to Have

  • Experience with optical interfaces (TIA/driver for photonics)
  • Familiarity with SerDes / PAM4 / coherent optics
  • Exposure to EM effects and layout-dependent parasitics
  • Lab bring-up and silicon validation experience

💰 Package

  • Competitive base + meaningful equity
  • Targeting $160k – $230k base (flexible for top candidates)
  • Strong upside in a high-growth start-up