R-
AMS Verification Lead (AMSV Lead)
Accepting applicationsRapinnoTech - APAC & USA · Bengaluru, Karnataka, India
Contract Mid_senior AnalogCadenceMentorMixed SignalMixed-Signal
Estimated market salary
₹24-44 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
18 Jun
Category
Verification
Experience
Mid_senior
Country
India
🚀 We're Hiring: AMS Verification Lead (AMSV Lead) – C2H 🚀
🏢 Payroll: Rapinno Tech
📍 Location: Bangalore (Work From Office)
💼 Role: AMS Verification Lead
⏳ Experience: 8–12 Years
📅 Employment Type: Full-Time
About the Role
We are looking for an experienced AMS Verification Lead with strong expertise in Analog Mixed Signal (AMS) verification methodologies, simulation environments, and team leadership. The ideal candidate will drive AMS verification activities, collaborate with cross-functional design teams, and contribute to advanced SoC/IP verification programs.
Key Responsibilities
✅ Develop and enhance AMS simulation methodologies and flows (AXUM, AVUM, UVM-AMS)
✅ Review specifications and create comprehensive verification plans
✅ Manage BOM and netlist generation processes
✅ Collaborate closely with Analog Design, Digital Design, and RTL teams to track updates and ensure alignment
✅ Plan work distribution within the team and execute critical verification tasks hands-on
✅ Run, analyze, and debug SPICE-based and digital simulations for AMS SoCs, IPs, and subsystems
✅ Understand analog and digital design intent, review simulation setups, and validate test conditions
✅ Analyze simulation results, debug functional mismatches, and identify root causes
✅ Develop behavioral models using Verilog-A/AMS, SV-RNM, and VHDL-AMS
✅ Optimize testbenches using Cadence, Xcelium, Synopsys, and related EDA platforms
✅ Improve verification productivity through automation, regression management, log parsing, and scripting
✅ Document verification findings, debug reports, and methodology improvements
✅ Mentor team members, lead debugging sessions, and contribute to technical excellence across the organization
Required Skills
🔹 Strong expertise in AMS Verification Methodologies
🔹 Hands-on experience in Mixed-Signal Simulation, Assertions, and Checker-Based Verification
🔹 Advanced knowledge of:
SystemVerilog
UVM
SV-RNM
Verilog-A
Verilog-AMS
Analog Behavioral Modeling
🔹 Strong fundamentals in Analog and Digital Design Concepts
🔹 Experience with:
Cadence Virtuoso
Synopsys VCS
Xcelium
SPICE Simulation Tools
🔹 Strong debugging and waveform analysis skills
🔹 Scripting expertise in:
Python
Perl
TCL
🔹 Excellent communication, leadership, and stakeholder management skills
📩 APPLY NOW
Interested candidates and referrals can share their updated resumes at:
📧 sreekanth.g@rapinnotech.com
Show more Show less
🏢 Payroll: Rapinno Tech
📍 Location: Bangalore (Work From Office)
💼 Role: AMS Verification Lead
⏳ Experience: 8–12 Years
📅 Employment Type: Full-Time
About the Role
We are looking for an experienced AMS Verification Lead with strong expertise in Analog Mixed Signal (AMS) verification methodologies, simulation environments, and team leadership. The ideal candidate will drive AMS verification activities, collaborate with cross-functional design teams, and contribute to advanced SoC/IP verification programs.
Key Responsibilities
✅ Develop and enhance AMS simulation methodologies and flows (AXUM, AVUM, UVM-AMS)
✅ Review specifications and create comprehensive verification plans
✅ Manage BOM and netlist generation processes
✅ Collaborate closely with Analog Design, Digital Design, and RTL teams to track updates and ensure alignment
✅ Plan work distribution within the team and execute critical verification tasks hands-on
✅ Run, analyze, and debug SPICE-based and digital simulations for AMS SoCs, IPs, and subsystems
✅ Understand analog and digital design intent, review simulation setups, and validate test conditions
✅ Analyze simulation results, debug functional mismatches, and identify root causes
✅ Develop behavioral models using Verilog-A/AMS, SV-RNM, and VHDL-AMS
✅ Optimize testbenches using Cadence, Xcelium, Synopsys, and related EDA platforms
✅ Improve verification productivity through automation, regression management, log parsing, and scripting
✅ Document verification findings, debug reports, and methodology improvements
✅ Mentor team members, lead debugging sessions, and contribute to technical excellence across the organization
Required Skills
🔹 Strong expertise in AMS Verification Methodologies
🔹 Hands-on experience in Mixed-Signal Simulation, Assertions, and Checker-Based Verification
🔹 Advanced knowledge of:
SystemVerilog
UVM
SV-RNM
Verilog-A
Verilog-AMS
Analog Behavioral Modeling
🔹 Strong fundamentals in Analog and Digital Design Concepts
🔹 Experience with:
Cadence Virtuoso
Synopsys VCS
Xcelium
SPICE Simulation Tools
🔹 Strong debugging and waveform analysis skills
🔹 Scripting expertise in:
Python
Perl
TCL
🔹 Excellent communication, leadership, and stakeholder management skills
📩 APPLY NOW
Interested candidates and referrals can share their updated resumes at:
📧 sreekanth.g@rapinnotech.com
Show more Show less