AMS Verification Engineer

Job Details

Job Description:

Develop and maintain behavioral models (BMods) for complex analog circuits (e.g. SerDes, PMU, DCDC) using SystemVerilog. - Support integration of BMods into the digital functional verification environment. - Debug and troubleshoot issues identified during functional verification or AMS simulations. - Run AMS simulations for improved coverage of AMS blocks, comparison to BMods, and full-chip power up simulations. - Lead code and simulation reviews. - Collaborate with analog designers, digital verification engineers, and system architects to ensure model accuracy and completeness. - Continuously improve modeling methodologies, simulation flows, and automation to increase team efficiency and coverage, leveraging AI-assisted tools (e.g. generative AI for code generation, AI-driven debugging, automated documentation) where applicable. - Explore and adopt modern AI-based workflows to accelerate BMod development, simulation analysis, and reporting.

Qualifications

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
At least 5 years of relevant experience in AMS verification, behavioral modeling, or analog/mixed-signal design.
In-depth knowledge of SystemVerilog for hardware modeling and verification, including User Defined Net Types (UDNTs).
Proven experience in developing behavioral models (BMods) for analog circuits using SystemVerilog, including translating circuit behavior into code for functional verification.
Experience running and debugging AMS simulations using industry-standard tools (e.g. Cadence Xcelium, Synopsys VCS-XA).
Strong debugging skills for identifying and resolving issues within BMods and AMS simulations.
Good communication skills and ability to work collaboratively in a multidisciplinary environment.
Ability to leverage modern AI-based tools and workflows (e.g. AI-assisted code generation, automated analysis) as part of daily modeling and verification tasks.

Advantages

Familiarity with integrating BMods into digital functional verification simulation environments.
Experience with power management circuits: LDO, DCDC converters, bandgap references, power-on-reset.
Background in SerDes design or verification: TX/RX, TDC, DTC, equalization.
Experience with scripting and automation (Python, Tcl, SKILL) for simulation flow management and AI-augmented productivity.
Understanding of full-chip power up sequences and mixed-signal interaction debugging.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business Group

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Show more Show less