AD
AMS Verification Engineer
Accepting applicationsACL Digital · Bengaluru, Karnataka, India
Full-Time Mid_senior SystemVerilogUVMAMSTestbenchSimulation
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Job Description
Position: AMS Verification Engineer
Location: Bengaluru, Karnataka, India
Employment Type: Full-time
Experience :3+Years
About the Role:
We are seeking an experienced and motivated AMS (Analog Mixed-Signal) Verification Engineer to join our chip design team. In this role, you will be responsible for defining verification strategies, developing mixed-signal testbenches, creating behavioral models, and ensuring functional correctness and robustness of complex analog/digital integrated circuits (ICs) and SoCs before tape-out.
Key Responsibilities:
Testbench Development & Verification Execution: Design, build, and maintain functional verification environments at both block and full-chip SoC levels using SystemVerilog/UVM and Verilog-AMS/SystemVerilog RNM (Real Number Modeling).
Verification Planning: Work closely with analog design, digital design, and architecture teams to review specs and author comprehensive verification plans and coverage metrics.
Behavioral Modeling: Write and validate high-level analog behavioral models (Verilog-AMS, SystemVerilog, wreal) to enable fast, efficient full-chip mixed-signal co-simulations.
Mixed-Signal Co-Simulation: Perform schematic/behavioral mixed-signal co-simulations using Cadence Virtuoso, Spectre, AMS Designer, or Synopsys XA/VCS tools.
Coverage & Debugging: Write functional assertions (SVA), define coverage goals, analyze regression results, and debug differences between analog implementations and reference models.
Automation & Scripting: Automate simulation flows, regression management, and report generation using Python, Perl, Tcl, or Shell scripts.
Show more Show less
Position: AMS Verification Engineer
Location: Bengaluru, Karnataka, India
Employment Type: Full-time
Experience :3+Years
About the Role:
We are seeking an experienced and motivated AMS (Analog Mixed-Signal) Verification Engineer to join our chip design team. In this role, you will be responsible for defining verification strategies, developing mixed-signal testbenches, creating behavioral models, and ensuring functional correctness and robustness of complex analog/digital integrated circuits (ICs) and SoCs before tape-out.
Key Responsibilities:
Testbench Development & Verification Execution: Design, build, and maintain functional verification environments at both block and full-chip SoC levels using SystemVerilog/UVM and Verilog-AMS/SystemVerilog RNM (Real Number Modeling).
Verification Planning: Work closely with analog design, digital design, and architecture teams to review specs and author comprehensive verification plans and coverage metrics.
Behavioral Modeling: Write and validate high-level analog behavioral models (Verilog-AMS, SystemVerilog, wreal) to enable fast, efficient full-chip mixed-signal co-simulations.
Mixed-Signal Co-Simulation: Perform schematic/behavioral mixed-signal co-simulations using Cadence Virtuoso, Spectre, AMS Designer, or Synopsys XA/VCS tools.
Coverage & Debugging: Write functional assertions (SVA), define coverage goals, analyze regression results, and debug differences between analog implementations and reference models.
Automation & Scripting: Automate simulation flows, regression management, and report generation using Python, Perl, Tcl, or Shell scripts.
Show more Show less