Q
AI20P RTL Engineer
Accepting applicationsQpisemi · Bengaluru, Karnataka, India
Full-Time Mid_senior SystemVerilogRTLMicroarchitectureAI AcceleratorMachine Learning
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
About the Role
Join a cutting-edge hardware development team to push the boundaries of Machine Learning by designing the Register-Transfer Level (RTL) for custom AI accelerators. You will co-design microarchitectures and write high-quality RTL code, shaping the next generation of computing infrastructure.
Core Responsibilities
Microarchitecture & Design: Define and document complex microarchitecture for TPU compute, networking, or control subsystems.
RTL Development: Develop performant, power-efficient, and synthesizable RTL code in SystemVerilog.
Verification Collaboration: Work closely with the Design Verification (DV) team to create test plans, debug RTL, and ensure functional correctness.
Physical Design Co-design: Partner with physical design teams to optimize logic for timing, area, power, and manufacturability.
Architecture & Power: Evaluate design features and hardware capabilities alongside architecture and power teams.
Tooling: Contribute to the continuous enhancement of internal design methodologies and automation flows.
Qualifications
Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
Experience: 3+ years of experience in high-performance ASIC RTL design, including clocking, reset, and timing-critical development.
Technical Skills: Proficiency in SystemVerilog and digital design fundamentals (e.g., synchronous/asynchronous logic, state machines).
Automation: Experience using scripting languages like Python, Tcl, or Perl for design automation and data analysis.
Teamwork: Strong track record of cross-functional collaboration with software, hardware, and architecture teams.
Show more Show less
Join a cutting-edge hardware development team to push the boundaries of Machine Learning by designing the Register-Transfer Level (RTL) for custom AI accelerators. You will co-design microarchitectures and write high-quality RTL code, shaping the next generation of computing infrastructure.
Core Responsibilities
Microarchitecture & Design: Define and document complex microarchitecture for TPU compute, networking, or control subsystems.
RTL Development: Develop performant, power-efficient, and synthesizable RTL code in SystemVerilog.
Verification Collaboration: Work closely with the Design Verification (DV) team to create test plans, debug RTL, and ensure functional correctness.
Physical Design Co-design: Partner with physical design teams to optimize logic for timing, area, power, and manufacturability.
Architecture & Power: Evaluate design features and hardware capabilities alongside architecture and power teams.
Tooling: Contribute to the continuous enhancement of internal design methodologies and automation flows.
Qualifications
Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
Experience: 3+ years of experience in high-performance ASIC RTL design, including clocking, reset, and timing-critical development.
Technical Skills: Proficiency in SystemVerilog and digital design fundamentals (e.g., synchronous/asynchronous logic, state machines).
Automation: Experience using scripting languages like Python, Tcl, or Perl for design automation and data analysis.
Teamwork: Strong track record of cross-functional collaboration with software, hardware, and architecture teams.
Show more Show less