AI for Chip Design Engineer (RTL & Architecture)

The mission

We are building AI agent hardware with AI agents. Not as a headline — as an engineering practice. The teams that build the right AI-augmented hardware design practices now will develop institutional knowledge that is extremely difficult to replicate. You build that methodology at Aramas from the ground up — on an Intel Agilex 7 FPGA platform, designing the IP blocks that make agent execution fast, efficient, and correct.

What you own

The AI-augmented hardware design workflow across the full chip development cycle — from architecture exploration through verification closure. FPGA IP design and integration across the AXU data path, including PCIe endpoint behavior, HBM memory controllers, and on-fabric compute blocks. A force multiplier on a small, elite hardware team that cannot afford to work the way a 500-person RTL organization works.

What you'll do

Design, implement, and verify custom FPGA IP blocks — from block-level RTL through timing closure and functional sign-off
Own PCIe endpoint design: TLP handling, completion logic, flow control, and BAR mapping for a high-throughput PCIe 5.0 interface
Drive timing closure across complex multi-clock designs, managing placement constraints, floorplanning, and critical path optimization
Apply AI-assisted RTL generation and code review to accelerate hardware block design and reduce manual iteration cycles
Build agent workflows for verification coverage closure, linting, and design correctness checks across fabric and interface subsystems
Own EDA toolchain integration with AI augmentation across synthesis, timing analysis, and functional verification flows
Evaluate and deploy AI tools for formal verification, assertion generation, and PCIe protocol compliance checking

What we're looking for

Strong RTL engineering foundation — SystemVerilog, UVM, formal verification fundamentals
Hands-on FPGA design experience on Intel/Altera (Stratix, Arria, Agilex) or Xilinx/AMD (UltraScale+, Versal) platforms — understands vendor-specific primitives, clock resources, and timing closure workflows
Proficient with vendor EDA toolchains — Quartus Prime / Questa or Vivado / Vitis; knows how to diagnose and close timing failures on large designs
Familiarity with PCIe protocol mechanics — TLP structure, credit-based flow control, completion handling, and BAR design; has debugged PCIe link behavior with a protocol analyzer
Hands-on experience with AI-assisted EDA tools or internal LLM tooling for hardware design
Understands the limits of AI-generated RTL — knows how to verify it rigorously, not just generate it quickly
Background at a semiconductor company, FPGA IP company, hyperscaler silicon team, or AI-EDA startup
Python fluency for toolchain scripting, agent workflow construction, and regression automation

Signal keywords

SystemVerilogUVMIntel Agilex / Xilinx UltraScale+Quartus / VivadoFPGA timing closurePCIe TLPPCIe 5.0AI-assisted EDAFormal verificationRTL generation
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