IT
AI Chiplet Virtual Platform Architect / Technical Lead
Accepting applicationsIravan Technologies · Pune City, Maharashtra, India
Full-Time Mid_senior AIC++PCIePythonRTL
Estimated market salary
₹7-12 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Designation-AI Chiplet Virtual Platform Architect / Technical Lead
Experience Level: 10–15+ Years
Role Type: Technical Lead / Architect
Location: Bangalore / Hyderabad (Hybrid)
Position Summary
Lead the architecture and development of a reusable AI Chiplet Virtual Platform / VDK for the company’s connectivity, memory, power, and chiplet infrastructure products and their integration with customer XPUs. This is the anchor architecture role for the team, and the person in this role sets the platform foundation that JD 2–7 build on.
Key Responsibilities
Customer XPU / Chiplet Architecture Analysis: Study customer XPU/SoC architecture, identify software-visible and performance-critical components, define virtualization requirements and model abstraction levels, and identify interfaces between the customer compute die and the company’s chiplets.
Virtual Platform / VDK Foundation: Architect and establish the Synopsys Virtualizer/VDK environment; develop reusable SystemC/TLM- based platform infrastructure; define platform configuration, component hierarchy, and interconnect architecture; establish reusable VP templates for different customer XPU configurations.
Multi-Chiplet / Multi-XPU Scalability: Define scalable virtual architectures representing multiple chiplets/XPUs, and support scale-up and multi-device configurations.
AI Infrastructure System Modelling: Define the complete system-level virtual platform architecture and integrate compute, connectivity, memory, power, and I/O models.
System Performance & Architecture Exploration: Work with performance architects to enable architecture trade-off studies.
RTL / VP / Emulation Correlation: Define the methodology for correlating TLM models with RTL and emulation.
Automated Regression & Performance Infrastructure: Define the overall VP validation and regression strategy.
Required Technical Skills
10–15+ years of semiconductor/system engineering experience.
Strong C++ and SystemC/TLM.
Synopsys Virtualizer / VDK experience.
SoC/system architecture and virtual prototyping.
PCIe / CXL / UCIe / AMBA.
Strong understanding of AI/HPC infrastructure.
Experience working with both RTL and software teams.
Preferred Skills
Chiplet architecture and HBM.
AI accelerator/XPU architecture.
Emulation platforms such as ZeBu / Palladium / Veloce.
Python automation.
Education
• B.E. / B.Tech / M.E. / M.Tech / M.S. in Electronics, Electrical, Computer Engineering, or related discipline.
Project Experience
• Demonstrated ownership of a virtual platform / VDK architecture used across multiple products or customer configurations.
• Experience defining platform architecture spanning compute, connectivity, memory, power, and I/O.
Soft Skills
Strong systems-thinking and architecture leadership across hardware, software, and verification teams.
Ability to translate customer XPU requirements into a virtual platform architecture.
Clear technical communication with RTL, software, and performance teams.
Good to Have
Prior experience architecting a virtual platform that shipped across more than one customer program.
Direct exposure to correlating TLM models against RTL/emulation results.
Expected Deliverables
Synopsys Virtualizer/VDK-based platform architecture and reusable VP templates.
System-level virtual platform integrating compute, connectivity, memory, power, and I/O models.
VP validation/regression strategy and RTL/emulation correlation methodology.
Interested candidates may share resumes at [email protected](Immediate to 30-day notice period candidates preferred).
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Experience Level: 10–15+ Years
Role Type: Technical Lead / Architect
Location: Bangalore / Hyderabad (Hybrid)
Position Summary
Lead the architecture and development of a reusable AI Chiplet Virtual Platform / VDK for the company’s connectivity, memory, power, and chiplet infrastructure products and their integration with customer XPUs. This is the anchor architecture role for the team, and the person in this role sets the platform foundation that JD 2–7 build on.
Key Responsibilities
Customer XPU / Chiplet Architecture Analysis: Study customer XPU/SoC architecture, identify software-visible and performance-critical components, define virtualization requirements and model abstraction levels, and identify interfaces between the customer compute die and the company’s chiplets.
Virtual Platform / VDK Foundation: Architect and establish the Synopsys Virtualizer/VDK environment; develop reusable SystemC/TLM- based platform infrastructure; define platform configuration, component hierarchy, and interconnect architecture; establish reusable VP templates for different customer XPU configurations.
Multi-Chiplet / Multi-XPU Scalability: Define scalable virtual architectures representing multiple chiplets/XPUs, and support scale-up and multi-device configurations.
AI Infrastructure System Modelling: Define the complete system-level virtual platform architecture and integrate compute, connectivity, memory, power, and I/O models.
System Performance & Architecture Exploration: Work with performance architects to enable architecture trade-off studies.
RTL / VP / Emulation Correlation: Define the methodology for correlating TLM models with RTL and emulation.
Automated Regression & Performance Infrastructure: Define the overall VP validation and regression strategy.
Required Technical Skills
10–15+ years of semiconductor/system engineering experience.
Strong C++ and SystemC/TLM.
Synopsys Virtualizer / VDK experience.
SoC/system architecture and virtual prototyping.
PCIe / CXL / UCIe / AMBA.
Strong understanding of AI/HPC infrastructure.
Experience working with both RTL and software teams.
Preferred Skills
Chiplet architecture and HBM.
AI accelerator/XPU architecture.
Emulation platforms such as ZeBu / Palladium / Veloce.
Python automation.
Education
• B.E. / B.Tech / M.E. / M.Tech / M.S. in Electronics, Electrical, Computer Engineering, or related discipline.
Project Experience
• Demonstrated ownership of a virtual platform / VDK architecture used across multiple products or customer configurations.
• Experience defining platform architecture spanning compute, connectivity, memory, power, and I/O.
Soft Skills
Strong systems-thinking and architecture leadership across hardware, software, and verification teams.
Ability to translate customer XPU requirements into a virtual platform architecture.
Clear technical communication with RTL, software, and performance teams.
Good to Have
Prior experience architecting a virtual platform that shipped across more than one customer program.
Direct exposure to correlating TLM models against RTL/emulation results.
Expected Deliverables
Synopsys Virtualizer/VDK-based platform architecture and reusable VP templates.
System-level virtual platform integrating compute, connectivity, memory, power, and I/O models.
VP validation/regression strategy and RTL/emulation correlation methodology.
Interested candidates may share resumes at [email protected](Immediate to 30-day notice period candidates preferred).
Show more Show less