NVIDIA
902 open semiconductor roles on SiliconBoard
Open positions at NVIDIA
Senior ASIC Methodology, Flow and Integration Engineer
2 Locations
Senior Manager, ASIC Chip Engineering
Santa Clara, United States, North America
Senior Mask Design Engineer – Hardware
North Carolina, United States
Senior Post-Silicon Characterization and Validation Methodology
Yokneam, Israel, Middle East
Senior System Software Engineer, SoC Power and Performance - O-RAN Infrastructure
3 Locations
ASIC TOP Floorplan Design Engineer
Shanghai, China, Asia
CAD Developer, IR, Timing and Physical Design Optimization
Shanghai, China, Asia
Senior DFT Methodology - Data Analytics and Applied AI Engineer
Santa Clara, United States, North America
DFT Verification Engineer
Bangalore, India, Asia
DFT Methodology Engineer
Santa Clara, CA
SOC Clocks RTL Design Engineer
3 Locations
Senior SOC Clocks RTL Design Engineer
2 Locations
Senior Chip Design and Verification Engineer
Tel Aviv, Israel, Middle East
Senior System Software Engineer - CPU SoC Boot Firmware
2 Locations
Senior ASIC Verification Engineer - PMU
Shanghai, China, Asia
SOC Design Engineer
Bengaluru, Karnataka, India
PCB Design EDA and AI Engineer - New College Graduate 2027
Shenzhen, China, Asia
Senior Design Verification Engineer
Bangalore, India, Asia
Senior Platform Safety Analysis Engineer, HALOs Platforms - Autonomous Vehicles
Columbia, SC
Senior Platform Safety Analysis Engineer, HALOs Platforms - Autonomous Vehicles
California, United States
Senior Architect, GPU and SoC Modelling
Bangalore, India, Asia
System Software Engineer - Performance Verification Infrastructure
Santa Clara, CA
Package Design Methodology Engineer
Austin, TX
Package Design Methodology Engineer
California, United States
Package Design Methodology Engineer
Santa Clara, CA
Senior System Test Engineer
Santa Clara, CA
System Software Engineer - Performance Verification Infrastructure
Westford, MA
Senior Software Engineer, SOC Design Methodology
Santa Clara, United States, North America
Senior Architect, SOC Modeling
Santa Clara, United States, North America
SoC Modelling Architect
2 Locations
ASIC Design Engineer - Hardware
Austin, TX
Senior Developer Technology Engineer - Agentic SoC Performance
Santa Clara, United States, North America
GPU Verification Engineer - New College Grad 2026
Westford, MA
DFX CAD Tools Development Engineer
Bengaluru, Karnataka, India
Manager, ASIC Chip - GPU
Santa Clara, United States, North America
Applied Research Engineer, Chip Design
Santa Clara, United States, North America
Senior ASIC Physical Design Engineer, Netlisting
Santa Clara, CA
Senior ASIC Physical Design Engineer, Netlisting
Austin, TX
Hardware Design Validation Engineer - Memory Subsystem
Santa Clara, CA
Verification Engineer - Networking IPs
Hyderabad, Telangana, India
Verification Engineer - Networking IPs
Bengaluru, Karnataka, India
CPU Verification Infrastructure Tools Architect
Bengaluru, Karnataka, India
Senior ASIC Hardware Design Engineer
Westford, MA
SoC Verification Lead
Santa Clara, CA
ESD and Latch-up Test Engineer
Santa Clara, CA
Verification Engineer - PCIE
Bengaluru, Karnataka, India
Software Engineer, Physical Design Infrastructure - New College Grad 2026
Santa Clara, CA
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
2 Locations
Senior ASIC Design Engineer - GPU
3 Locations
Software R&D Engineer, VLSI Physical Design - New College Grad 2026
Santa Clara, CA
ASIC Physical Design and Timing Engineer - New College Grad 2026
Santa Clara, CA
Senior ASIC Design Engineer - GPU
Hillsboro, OR
Senior ASIC Design Engineer - GPU
Durham, NC
Senior Physical Design and Timing Engineer
Durham, NC
Senior Physical Design and Timing Engineer
Hillsboro, OR
Senior Physical Design and Timing Engineer
Austin, TX
ASIC Design Engineer, BOOT and Power Management
Hyderabad, Telangana, India
ASIC Design Engineer, BOOT and Power Management
Bengaluru, Karnataka, India
Verification Engineer - Memory Subsystem
Bengaluru, Karnataka, India
DFT Engineer - Hardware
Bengaluru, Karnataka, India
Senior Software R&D Engineer, VLSI Physical Design
Santa Clara, CA
Senior SOCD Applied AI Engineer
Santa Clara, CA
Verification Engineer, Performance
Bengaluru, Karnataka, India
RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, United States, North America
Chip Design and Verification Engineer
Tel Aviv, Israel, Middle East
Senior Chip Design Verification Engineer
Beer Sheva, Israel, Middle East
Senior Digital Design Engineer - High-Speed I/O and Photonics
Santa Clara, CA
Senior Photonic Layout Design Engineer
Santa Clara, CA
Analog Mask Design Engineer
Bengaluru, Karnataka, India
Mechanical Product Engineer
New Delhi, Delhi, India
Senior Full-Stack Software Engineer - VLSI Tools
Santa Clara, CA
Lead Hardware Design Validation Engineer - Memory Subsystem
Santa Clara, CA
Lead Hardware Design Validation Engineer
Santa Clara, CA
Senior ASIC Design Engineer - Agentic AI
Santa Clara, CA
Senior ASIC Design Engineer - Agentic AI
Durham, NC
Senior DevOps Software Engineer - Chip Design
2 Locations
Senior Verification Engineer, Switch SoC
Bangalore, India, Asia
Senior Circuit Methodology Engineer
Santa Clara, CA
Senior Product Development Engineer - Datacenter
Santa Clara, CA
Senior Deep Learning Performance Architect
Redmond, WA
PCIe IP Verification Engineer
Bengaluru, Karnataka, India
DFT Engineer
Bengaluru, Karnataka, India
Senior GPU Floorplan Design Engineer
Bengaluru, Karnataka, India
Senior Package Layout Engineer - Hardware
Bengaluru, Karnataka, India
Senior System Integration and Validation Engineer
Bengaluru, Karnataka, India
Software QA Test Developer - Windows Devices Validation
Hyderabad, Telangana, India
Senior SOC Verification Engineer - Networking
Bengaluru, Karnataka, India
IP Verification Engineer - GPU Core Pipeline
Bengaluru, Karnataka, India
Verification Engineer - GPU Fullchip
Bengaluru, Karnataka, India
Senior ASIC Timing Engineer, DFT
Santa Clara, United States, North America
Senior Design Verification Engineer - Hardware
Shanghai, China, Asia
Distinguished Engineer - Memory Architecture
Austin, TX
CPU Design Methodology Engineer
Arizona, United States
CPU Design Methodology Engineer
Austin, TX
CPU Design Methodology Engineer
Hillsboro, OR
Test and Failure Analysis Technician
Santa Clara, CA
CPU Design Methodology Engineer
Santa Clara, CA
Senior C++ Software Engineer
Santa Clara, CA
Physical Design Engineer
Westford, MA
Distinguished Engineer - Memory Architecture
Santa Clara, CA
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