Intel
387 open semiconductor roles on SiliconBoard
Open positions at Intel
Sr. Principal Engineer, Physical Design
Santa Clara, United States, North America
SoC Logic Design Engineer
Bangalore, India, Asia
SoC Logic Design Engineer
3 Locations
Senior SoC Electrical Validation and Tuning Engineer
Bangalore, India, Asia
Package Assembly Low Yield Analysis Engineer
Phoenix, United States, North America
Experienced IP Logic Design Engineer
San Jose, United States, North America
Analog Design Architect
Bangalore, India, Asia
Logic Design Engineer
Bangalore, India, Asia
Design Verification Engineer
Bangalore, India, Asia
Formal Verification Engineer - CPU Core
Folsom, United States, North America
Senior CPU Core Physical Design Engineer
Folsom, United States, North America
Wafer Assembly TD Strategic Program Manager
Hillsboro, United States, North America
APTM Yield Analysis/Device Engineer
Albuquerque, United States, North America
Analog Layout Design Engineer
Bangalore, India, Asia
SoC RTL Verification Intern
Shanghai, China, Asia
Design Emulation Engineer
Virtual Canada, Canada, North America
Mixed Signal Logic Design Engineer
Bangalore, India, Asia
Pre-Silicon Validation Engineer
Bangalore, India, Asia
Silicon SoC Architect
Bangalore, India, Asia
Assembly Equipment Group Department Manager
Ho Chi Minh City, Vietnam, Asia
IP Design Verification Engineer
Penang, Malaysia, Asia
CAD Engineer for CPU Logic Design and Validation
Austin, TX
Senior CPU Pre-Silicon Verification Engineer
Austin, TX
Yield Platform Analyst
2 Locations
APTD Substrate Quality Engineer
Phoenix, United States, North America
Formal Verification Student
Haifa, Israel, Middle East
Design Verification Engineering Intern
Virtual Canada, Canada, North America
TD Media and Collaterals Development Engineer
Phoenix, United States, North America
Soc Functional Validation Engineer
Phoenix, United States, North America
DFT Lead (Scan/ATPG) Engineer
Bangalore, India, Asia
Principal Engineer, SoC Design Verification
Bangalore, India, Asia
Physical Design Engineer - Neuromorphic Computing
Folsom, CA
Physical Design Engineer - Neuromorphic Computing
Hillsboro, OR
Physical Design Engineer - Neuromorphic Computing
Santa Clara, CA
Physical Design Engineer - Neuromorphic Computing
San Jose, CA
GPU Physical Design Engineer Lead
Santa Clara, CA
GPU Physical Design Engineer Lead
Folsom, CA
Clocking / Physical Design Engineer
Austin, United States, North America
Senior Physical Design Application Engineer
Santa Clara, CA
CPU Physical Design Automation Engineer
Austin, TX
Senior Yield Engineer – Substrate & Advanced Packaging
Phoenix, United States, North America
Principal Analog Circuit Design Engineer - SerDes
Toronto, Canada, North America
EDA Tools Software Engineer
3 Locations
Post Silicon Validation Engineer
Haifa, Israel, Middle East
Pre-Silicon Verification Engineer
Austin, TX
Senior Physical Design Application Engineer
Hillsboro, OR
WLA Yield Defect Metrology Engineer - Shift 7
Hillsboro, United States, North America
WLA Yield Defect Metrology Engineer
Hillsboro, United States, North America
Principal Analog Circuit Design Engineer - SerDes
3 Locations
SoC Debug Engineer
Guadalajara, Mexico, North America
Strategic Account Manager - Google Account
Santa Clara, United States, North America
Lead CPU Design Engineer
Phoenix, AZ
Pre-Silicon Verification Engineer
Phoenix, AZ
Senior Physical Design Application Engineer
Phoenix, AZ
Yield Development Engineer
Phoenix, United States, North America
SOC Functional Validation Engineer- Security
Bangalore, India, Asia
Graduate Talent (IP Design Verification Engineer)
2 Locations
Graduate Talent (IP Logic Design Engineer)
2 Locations
Physical Design Timing Engineer
4 Locations
Facility Category Manager
2 Locations
Manufacturing Operator (Contract)
Penang, Malaysia, Asia
CPU RTL Design Engineer
Phoenix, AZ
CPU RTL Design Engineer
Austin, TX
GPU Logic Design Engineer
Folsom, CA
Qubit Control IC Designer
Hillsboro, OR
Module Development Engineer- Hybrid Bonding
Hillsboro, OR
APTM Advanced Packaging Dry Etch Development Manager
Hillsboro, United States, North America
Substrates Supply Manager
3 Locations
NMSi - F11x Production Line Coordinator Technician Contract (Day Shift)
Albuquerque, United States, North America
WPM- F9 Production Line Coordinator Technician Contract (Night Shift)
Albuquerque, United States, North America
WPM- C4 Production Line Coordinator Technician Contract (Swing Shift)
Albuquerque, United States, North America
Strategic Account Executive – Telecommunications
Virtual Mexico, Mexico, North America
Fab Equipment Maintenance Commodity Manager
4 Locations
Senior CPU Physical Design Engineer
Austin, United States, North America
CPU Design and Verification Student Worker
Guadalajara, Mexico, North America
SoC Design Engineer Intern
San Jose, United States, North America
Verification Engineer Intern
San Jose, United States, North America
Manufacturing Systems Engineer
Penang, Malaysia, Asia
Graduate Talent (Analog Layout Engineer)
2 Locations
Supply Chain Material Program Manager
Chengdu, China, Asia
SOC Physical Design Static Timing Analysis Engineer
Santa Clara, CA
SOC Physical Design Static Timing Analysis Engineer
Phoenix, AZ
Senior Pre-Silicon Verification Engineer
Phoenix, AZ
Senior Pre-Silicon Verification Engineer
Boxborough, MA
Senior Pre-Silicon Verification Engineer
Hillsboro, OR
Senior Pre-Silicon Verification Engineer
Austin, TX
Design Engineer - Neuromorphic Computing
Phoenix, AZ
Senior RTL Design Engineer
Phoenix, AZ
CPU Microcode Design Engineer
Hillsboro, OR
Silicon Packaging Design Engineer
Phoenix, AZ
CPU Microcode Design Engineer
Austin, TX
Senior CPU Microcode Design Engineer
Austin, TX
Senior CPU Microcode Design Engineer
Hillsboro, OR
Design Engineer - Neuromorphic Computing
Hillsboro, OR
CPU Formal Verification Engineer
Phoenix, AZ
Design Verification Engineer
Phoenix, AZ
Design Verification Engineer
Austin, TX
Junior CPU Design Verification Engineer
Hillsboro, OR
Junior CPU Design Verification Engineer
Austin, TX
CPU Verification Engineer
Austin, TX
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